SDI-FMC User Manual
25
April 22, 2019
SDI_3G_TX_p0
C2
SDI 3G Transmitter
Channel 0
Output
VCCADJ
SDI_3G_TX_n0
C3
SDI 3G Transmitter
Channel 0
Output
VCCADJ
SDI_3G_TX_p1
A30
SDI 3G Transmitter
Channel 1
Output
VCCADJ
SDI_3G_TX_n1
A31
SDI 3G Transmitter
Channel 1
Output
VCCADJ
SDI_3G_RX_p0
C6
SDI 3G Receiver
Channel 0
Input
VCCADJ
SDI_3G_RX_n0
C7
SDI 3G Receiver
Channel 0
Input
VCCADJ
SDI_3G_RX_p1
A10
SDI 3G Receiver
Channel 1
Input
VCCADJ
SDI_3G_RX_n1
A11
SDI 3G Receiver
Channel 1
Input
VCCADJ
3
3
.
.
2
2
U
U
s
s
i
i
n
n
g
g
t
t
h
h
e
e
1
1
2
2
G
G
S
S
D
D
I
I
shows the system block diagram of the 12G SDI. The M23145 Reclocker chips and
MACD23528 Cable Driver chips are used to transmit the 12G SDI signal and the M23554 Cable
Equalizer chips are used to receive the 12G SDI signal. The M23145 and M23554 are directly
connected to the FPGA transceiver pins. The BNC connecters are used as an interface to connect
the external 12G SDI signals. Besides the 12G SDI signal, these chips also support the
6G/3G/HD/SD SDI signals.
The six 12G-SDI chips are connected through an SPI daisy chain (seeing green line in
).
Developers can communicate with these chips through the SPI interface. Due to the NDA limitation
(for detail information about how to control the 12G SDI chips) please contact the chip vender
MACOM
Company.
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