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Terasic DE10-Agiles, User Manual

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Terasic DE10-Agiles User Manual Download Page 58

 

 

 

 

DE10-Agilex   
User Manual 

58 

 

www.terasic.com

 

January 29, 

2021 

 

 

 

p 

QSFPDDB_REFCLK_n 

QSFP-DD port transceiver 

reference clock n 

LVDS 

PIN_A

P

13 

QSFPDDB_INITMODE 

Initialization mode 

1.2V 

PIN_DA18 

QSFPDDB_INTERRUPT_n 

Interrupt 

1.2V 

PIN_DC18 

QSFPDDB_MOD_PRS_n 

Module Present 

1.2V 

PIN_CY19 

QSFPDDB_MOD_SEL_n 

Module Select 

1.2V 

PIN_CR22 

QSFPDDB_RST_n 

Module Reset 

1.2V 

PIN_CU22 

QSFPDDB_SCL 

2-wire serial interface clock 

1.2V 

PIN_CY17 

QSFPDDB_SDA 

2-wire serial interface data 

1.2V 

PIN_H19   

 

2.8 

 

PCI Express 

The  FPGA  development  board  is  designed  to fit  entirely  into  a  PC motherboard  with 

x16  PCI  Express  slot.  Utilizing  built-in  transceivers  on  an  Agilex  device,  it  is  able  to 

provide a fully integrated PCI Express-compliant solution for multi-lane (x1, x4, x8 and 

x16) applications. With the PCI Express hard IP block incorporated in the Agilex device, 

it  will  allow  users  to  implement  simple  and  fast  protocol,  as  well  as  saving  logic 

resources  for  logic  application. 

Figure  2-18

  presents  the  pin  connection  established 

between the Agilex FPGA and PCI Express. 

 

The  PCI  Express  interface  supports  complete  PCI  Express  Gen1  at  2.5Gbps/lane, 

Gen2  at  5.0Gbps/lane,  Gen3  at  8.0Gbps/lane  and  Gen4  at  16.0Gbps/lane  protocol 

stack solution compliant to PCI Express base specification 4.0 that includes PHY-MAC, 

Data Link, and transaction layer circuitry embedded in PCI Express hard IP blocks. 

 

Please  note  that  it  is  a  requirement  that  you  connect  the  PCIe  external  power 

connector 8-pin 12V DC power connector in the FPGA to avoid FPGA damage due to 

insufficient power. The PCIE_REFCLK_p signal is a differential input that is driven from 

the  PC  motherboard  on  this  board  through  the  PCIe  edge  connector.  A  DIP  switch 

(SW6) is connected to the PCI Express to allow different configurations to enable x1, 

x4, x8 or x16 PCIe lane. 

 

Table 2-19 

summarizes the PCI Express pin assignments of the signal names relative 

to the Agilex FPGA. 

Summary of Contents for DE10-Agiles

Page 1: ...DE10 Agilex User Manual 1 www terasic com January 29 2021 1 1 Q...

Page 2: ...tures 6 1 3 Block Diagram 8 1 4 Board Power On 9 1 5 Board Protection 11 Chapter 2 Board Component 12 2 1 Board Overview 12 2 2 Configuration 13 2 3 Status and Setup Components 16 2 4 General User Inp...

Page 3: ...9 4 2 CFI Flash Memory Map 81 4 3 Programming Bit Stream File Into CFI Flash 82 4 4 Restore Factory Settings 85 4 5 Flash_Factory Example 86 4 6 Flash_User Example 88 Chapter 5 Peripheral Reference De...

Page 4: ...Express Library API 125 7 5 PCIe Reference Design Fundamental 130 7 6 PCIe Reference Design DDR4 139 Chapter 8 PCI Express Reference Design for Linux 151 8 1 PCI Express System Infrastructure 151 8 2...

Page 5: ...Testing by Transceiver Test Code 173 9 4 100G Ethernet Example E Tile FPGA 176 9 5 Serial Lite IV IP Example 182 Chapter 10 Dashboard GUI 193 10 1 Driver Installed on Host 194 10 2 Run Dashboard GUI 1...

Page 6: ...er performance 40 lower power for equivalent performance The accelerator includes PCI Express Gen 4 0 x16 two 200G QSFP DD connectors and offers 32GB of DDR4 up to 680Gbps bandwidth to provide adaptab...

Page 7: ...USB Blaster II or JTAG header for use with the Quartus Prime Programmer MAX10 FPGA 10M04SCU169 System Controller and Avalon ST x16 for configuration AS x4 configuration via EPCQ L configuration devic...

Page 8: ...System Monitor and Control Dashboard System for System Management Implement by System M AX10 FPGA Temperature sensor Fan control Power monitor Power Source PCI Express 8 pin DC 12V power PCI Express e...

Page 9: ...CIe slot This section will introduce how to power on the board and the information that user should notice in these two modes Stand alone Mode When the DE10 Agilex board is used in stand alone mode us...

Page 10: ...hough the Host can provide power to DE10 Agilex board via PCIe slot but Terasic strongly recommends that users connect an external power through the 2x4 ATX power connector to the board This can preve...

Page 11: ...r manual is provided in the system CD to allow users to monitor the temperature status of the board A temperature monitor IP see section 5 4 in the user manual is also provided so that the user can di...

Page 12: ...he DE10 Agilex 2 1 Board Overview Figure 2 1 and Figure 2 2 is the top and bottom view of the DE10 Agilex development board It depicts the layout of the board and indicates the location of the connect...

Page 13: ...ethods for the Intel Agilex FPGA Avalon ST x16 JTAG Active Serial AS normal and fast modes Need to Install Flash by user To switch these methods on the DE10 Agilex board the user needs to switch the M...

Page 14: ...10 Agilex board the System MAX10 FPGA on the board used as an external host will read the configuration file in the Flash and then programming the data into the FPGA through the Avalon ST protocol On...

Page 15: ...ing procedures show how to download a configuration bit stream into the Agilex FPGA Make sure that power is provided to the FPGA board Connect your PC to the FPGA board using a Mini USB cable and make...

Page 16: ...gh JTAG interface The SDM in the FPGA will emulate AS programming The manufacturer and part number of the serial flash are Micron and MT25QU128ABA8E12 0SIT Figure 2 5 Block diagram of the Active seria...

Page 17: ...wer is active D13 3 3 V Power Illuminates when 3 3 V power is active D11 FAN_ALERT_n Illuminates when the fan is abnormal such as when the fan speed is different from expected D7 MAX_CONF_DONE Illumin...

Page 18: ...and power sequence process finished 1 D1 POWER_LEDR Illuminates when the 3 3V power abnormal or power sequence process failed 1 D16 JTAG_RX Illuminates when the USB Blaster II circuit is transmitting...

Page 19: ...ct Off SW8 3 PCIE_PRSNT2n_x8 On Enable x8 presence detect Off Disable x8 presence detect Off SW8 4 PCIE_PRSNT2n_x16 On Enable x16 presence detect Off Disable x16 presence detect On Setup Configure Mod...

Page 20: ...ault 1 0 1 AS Fast mode for CvP 2 0 0 1 2 User need to solder a QSPI flash on the board by oneself Select Flash Image for Configuration One of the position of slide switch SW6 is used to specify the i...

Page 21: ...y OSC that can provide two frequencies to a 1 4 clock buffer then it will be fan out to four of differential clock pairs to the FPGA These four pair of clocks used as reference clocks for four DDR4 SO...

Page 22: ...ce Clock Switch Table 2 4 SW5 DIP Switch SW5 Position Reference Clock Frequency for DDR4 SO DIMM OFF Default 166 667Mhz ON 300Mhz 2 4 General User Input Output This section describes the user I O inte...

Page 23: ...sh buttons The FPGA board includes two user defined push buttons that allow users to interact with the Agilex device Each push button provides a high logic level or a low logic level when it is not pr...

Page 24: ...ard Reference Schematic Signal Name Description I O Standard Agilex Pin Number PB3 CPU_RESET_n High Logic Level when the button is not pressed 1 2V PIN_G56 User Defined Dip Switch There are two positi...

Page 25: ...LED ON Driving a logic 1 on the I O port turns the LED OFF 1 2V PIN_CR54 LED1 LED1 1 2V PIN_DB57 LED2 LED2 1 2V PIN_CY57 LED3 LED3 1 2V PIN_CU52 Table 2 9 User LEDs Pin Assignments Schematic Signal Na...

Page 26: ...Bi direction 1 2V GPIO 1 2V PIN_CT25 GPIO_P2 Bi direction 1 2V GPIO 1 2V PIN_CT17 GPIO_P3 Bi direction 1 2V GPIO 1 2V PIN_DC20 GPIO_CLK0 FPGA dedicated clock input or Bi direction 1 2V GPIO 1 2V PIN_C...

Page 27: ...0As to generate many frequencies to each QSFP DD port For memory interface the board provide a dual frequency OSC 166 667M and 300 MHz and fan out it to four different clocks to the Agilex FPGA via cl...

Page 28: ...er application CLK_50_B3A 1 2V PIN_G52 User application CLK_50_B3C 1 2V PIN_G26 User application Y8 CLK_100_B2A_p 100 0MHz LVDS PIN_CU50 User application Y4 OSC_CLK_1 125MHz LVDS PIN_CC60 User supplie...

Page 29: ...I5340A_LOL 1 2V PIN_CT19 Si5340A loss of lock This pin indicates when the DSPLL is locked high or out of lock low SI5340A_LOS_XAXB 1 2V PIN_CV19 Si5340A loss of XA XB signal SI5340A_RST_n 1 2V PIN_CU2...

Page 30: ...2 15 and Table 2 16 Table 2 13 DDR4 A Bank Pin Assignments Schematic Signal Names and Functions Schematic Signal Name Description I O Standard Agilex Pin Number DDR4A_DQ0 Data 0 1 2V POD PIN_W12 DDR4A...

Page 31: ...2V POD PIN_T5 DDR4A_DQ22 Data 22 1 2V POD PIN_V5 DDR4A_DQ23 Data 23 1 2V POD PIN_U10 DDR4A_DQ24 Data 24 1 2V POD PIN_N16 DDR4A_DQ25 Data 25 1 2V POD PIN_L12 DDR4A_DQ26 Data 26 1 2V POD PIN_M17 DDR4A_...

Page 32: ...DDR4A_DQ55 Data 55 1 2V POD PIN_W30 DDR4A_DQ56 Data 56 1 2V POD PIN_V23 DDR4A_DQ57 Data 57 1 2V POD PIN_V19 DDR4A_DQ58 Data 58 1 2V POD PIN_U24 DDR4A_DQ59 Data 59 1 2V POD PIN_U20 DDR4A_DQ60 Data 60 1...

Page 33: ...L 1 2V POD PIN_B29 DDR4A_DQS_n4 Data Strobe n 4 DIFFERENTIAL 1 2V POD PIN_D29 DDR4A_DQS5 Data Strobe p 5 DIFFERENTIAL 1 2V POD PIN_M29 DDR4A_DQS_n5 Data Strobe n 5 DIFFERENTIAL 1 2V POD PIN_P29 DDR4A_...

Page 34: ...DDR4A_A0 Address 0 SSTL 12 PIN_F17 DDR4A_A1 Address 1 SSTL 12 PIN_H17 DDR4A_A2 Address 2 SSTL 12 PIN_G16 DDR4A_A3 Address 3 SSTL 12 PIN_J16 DDR4A_A4 Address 4 SSTL 12 PIN_F15 DDR4A_A5 Address 5 SSTL...

Page 35: ...4A_CKE0 Clock Enable pin SSTL 12 PIN_A14 DDR4A_CKE1 Clock Enable pin SSTL 12 PIN_C14 DDR4A_ODT0 On Die Termination SSTL 12 PIN_B15 DDR4A_ODT1 On Die Termination SSTL 12 PIN_D15 DDR4A_CS_n0 Chip Select...

Page 36: ...N_G44 DDR4B_DQ3 Data 3 1 2V POD PIN_F41 DDR4B_DQ4 Data 4 1 2V POD PIN_H45 DDR4B_DQ5 Data 5 1 2V POD PIN_F45 DDR4B_DQ6 Data 6 1 2V POD PIN_H41 DDR4B_DQ7 Data 7 1 2V POD PIN_G40 DDR4B_DQ8 Data 8 1 2V PO...

Page 37: ...a 36 1 2V POD PIN_H61 DDR4B_DQ37 Data 37 1 2V POD PIN_C54 DDR4B_DQ38 Data 38 1 2V POD PIN_B55 DDR4B_DQ39 Data 39 1 2V POD PIN_D59 DDR4B_DQ40 Data 40 1 2V POD PIN_U48 DDR4B_DQ41 Data 41 1 2V POD PIN_V4...

Page 38: ...P51 DDR4B_DQ69 Data 69 1 2V POD PIN_M47 DDR4B_DQ70 Data 70 1 2V POD PIN_L52 DDR4B_DQ71 Data 71 1 2V POD PIN_N52 DDR4B_DQS0 Data Strobe p 0 DIFFERENTIAL 1 2V POD PIN_G42 DDR4B_DQS_n0 Data Strobe n 0 DI...

Page 39: ...1 2V POD PIN_W56 DDR4B_DQS8 Data Strobe p 8 DIFFERENTIAL 1 2V POD PIN_M49 DDR4B_DQS_n8 Data Strobe n 8 DIFFERENTIAL 1 2V POD PIN_P49 DDR4B_DBI_n0 Data Bus Inversion 0 1 2V POD PIN_F43 DDR4B_DBI_n1 Da...

Page 40: ...ddress 11 SSTL 12 PIN_W38 DDR4B_A12 Address 12 SSTL 12 PIN_P41 DDR4B_A13 Address 13 SSTL 12 PIN_L42 DDR4B_A14 Address 14 WE_n SSTL 12 PIN_N42 DDR4B_A15 Address 15 CAS_n SSTL 12 PIN_M43 DDR4B_A16 Addre...

Page 41: ...B_EVENT_n Chip Temperature Event 1 2 V PIN_J56 DDR4B_SDA Chip I2C Serial Data Bus 1 2 V PIN_H57 DDR4B_SCL Chip I2C Serial Clock 1 2 V PIN_H55 DDR4B_REFCLK_p DDR4 A port Reference Clock p True Differen...

Page 42: ...POD PIN_CE22 DDR4C_DQ18 Data 18 1 2V POD PIN_CG18 DDR4C_DQ19 Data 19 1 2V POD PIN_CH17 DDR4C_DQ20 Data 20 1 2V POD PIN_CF17 DDR4C_DQ21 Data 21 1 2V POD PIN_CE18 DDR4C_DQ22 Data 22 1 2V POD PIN_CG22 DD...

Page 43: ...ta 51 1 2V POD PIN_CF3 DDR4C_DQ52 Data 52 1 2V POD PIN_CE8 DDR4C_DQ53 Data 53 1 2V POD PIN_CH7 DDR4C_DQ54 Data 54 1 2V POD PIN_CE4 DDR4C_DQ55 Data 55 1 2V POD PIN_CH3 DDR4C_DQ56 Data 56 1 2V POD PIN_C...

Page 44: ...V POD PIN_CN20 DDR4C_DQS_n3 Data Strobe n 3 DIFFERENTIAL 1 2V POD PIN_CL20 DDR4C_DQS4 Data Strobe p 4 DIFFERENTIAL 1 2V POD PIN_CH13 DDR4C_DQS_n4 Data Strobe n 4 DIFFERENTIAL 1 2V POD PIN_CF13 DDR4C_D...

Page 45: ...Data Bus Inversion 7 1 2V POD PIN_CM5 DDR4C_DBI_n8 Data Bus Inversion 8 1 2V POD PIN_DC26 DDR4C_A0 Address 0 SSTL 12 PIN_CV15 DDR4C_A1 Address 1 SSTL 12 PIN_CT15 DDR4C_A2 Address 2 SSTL 12 PIN_CU14 D...

Page 46: ...V SSTL PIN_CY11 DDR4C_CK1 Clock p SSTL 12 PIN_CV3 DDR4C_CK_n1 Clock n SSTL 12 PIN_CT3 DDR4C_CKE0 Clock Enable pin SSTL 12 PIN_DC12 DDR4C_CKE1 Clock Enable pin SSTL 12 PIN_DA12 DDR4C_ODT0 On Die Termin...

Page 47: ...lex Pin Number DDR4D_DQ0 Data 0 1 2V POD PIN_CF57 DDR4D_DQ1 Data 1 1 2V POD PIN_CG56 DDR4D_DQ2 Data 2 1 2V POD PIN_CG52 DDR4D_DQ3 Data 3 1 2V POD PIN_CH53 DDR4D_DQ4 Data 4 1 2V POD PIN_CF53 DDR4D_DQ5...

Page 48: ...1 2V POD PIN_CY43 DDR4D_DQ33 Data 33 1 2V POD PIN_DA42 DDR4D_DQ34 Data 34 1 2V POD PIN_DC38 DDR4D_DQ35 Data 35 1 2V POD PIN_DA38 DDR4D_DQ36 Data 36 1 2V POD PIN_DB43 DDR4D_DQ37 Data 37 1 2V POD PIN_D...

Page 49: ...Data 65 1 2V POD PIN_CR42 DDR4D_DQ66 Data 66 1 2V POD PIN_CT43 DDR4D_DQ67 Data 67 1 2V POD PIN_CV43 DDR4D_DQ68 Data 68 1 2V POD PIN_CR38 DDR4D_DQ69 Data 69 1 2V POD PIN_CT39 DDR4D_DQ70 Data 70 1 2V PO...

Page 50: ...PIN_CY33 DDR4D_DQS7 Data Strobe p 7 DIFFERENTIAL 1 2V POD PIN_CV33 DDR4D_DQS_n7 Data Strobe n 7 DIFFERENTIAL 1 2V POD PIN_CT33 DDR4D_DQS8 Data Strobe p 8 DIFFERENTIAL 1 2V POD PIN_CU40 DDR4D_DQS_n8 Da...

Page 51: ...PIN_CE34 DDR4D_A8 Address 8 SSTL 12 PIN_CH35 DDR4D_A9 Address 9 SSTL 12 PIN_CF35 DDR4D_A10 Address 10 SSTL 12 PIN_CG36 DDR4D_A11 Address 11 SSTL 12 PIN_CE36 DDR4D_A12 Address 12 SSTL 12 PIN_CK39 DDR4D...

Page 52: ...gister ALERT_n output 1 2 V PIN_CN42 DDR4D_ACT_n Activation Command Input SSTL 12 PIN_CL32 DDR4D_RESET_n Chip Reset 1 2 V PIN_CK31 DDR4D_EVENT_n Chip Temperature Event 1 2 V PIN_CY53 DDR4D_SDA Chip I2...

Page 53: ...the QSFP DD port A and B pin assignments and signal names relative to the Agilex device Table 2 17 QSFP DD Port A Pin Assignments Schematic Signal Names and Functions Schematic Signal Name Description...

Page 54: ...inverted data of channel 6 High Speed Differential I O PIN_BR4 QSFPDDA_TX_n6 Transmitter inverted data of channel 6 High Speed Differential I O PIN_BT5 QSFPDDA_TX_p7 Transmitter non inverted data of c...

Page 55: ...Speed Differential I O PIN_BR10 QSFPDDA_RX_n6 Receiver inverted data of channel 6 High Speed Differential I O PIN_BT11 QSFPDDA_RX_p7 Receiver non inverted data of channel 7 High Speed Differential I...

Page 56: ...igh Speed Differential I O PIN_AM5 QSFPDDB_TX_p3 Transmitter non inverted data of channel 3 High Speed Differential I O PIN_AR4 QSFPDDB_TX_n3 Transmitter inverted data of channel 3 High Speed Differen...

Page 57: ...rential I O PIN_AR10 QSFPDDB_RX_n3 Receiver inverted data of channel 3 High Speed Differential I O PIN_AT11 QSFPDDB_RX_p4 Receiver non inverted data of channel 4 High Speed Differential I O PIN_AV7 QS...

Page 58: ...users to implement simple and fast protocol as well as saving logic resources for logic application Figure 2 18 presents the pin connection established between the Agilex FPGA and PCI Express The PCI...

Page 59: ...smit bus HIGH Speed Differential I O PIN_BR56 PCIE_TX_p1 Add in card transmit bus HIGH Speed Differential I O PIN_BN52 PCIE_TX_n1 Add in card transmit bus HIGH Speed Differential I O PIN_BM53 PCIE_TX_...

Page 60: ...Differential I O PIN_AY53 PCIE_TX_p8 Add in card transmit bus HIGH Speed Differential I O PIN_AV55 PCIE_TX_n8 Add in card transmit bus HIGH Speed Differential I O PIN_AW56 PCIE_TX_p9 Add in card trans...

Page 61: ...PCIE_RX_n0 Add in card receive bus HIGH Speed Differential I O PIN_BR62 PCIE_RX_p1 Add in card receive bus HIGH Speed Differential I O PIN_BN58 PCIE_RX_n1 Add in card receive bus HIGH Speed Differenti...

Page 62: ...Differential I O PIN_AU58 PCIE_RX_n9 Add in card receive bus HIGH Speed Differential I O PIN_AT59 PCIE_RX_p10 Add in card receive bus HIGH Speed Differential I O PIN_AP61 PCIE_RX_n10 Add in card recei...

Page 63: ...t plug detect x1 PCIe slot enabled using SW6 dip switch PCIE_PRSNT2n_x4 Hot plug detect x4 PCIe slot enabled using SW6 dip switch PCIE_PRSNT2n_x8 Hot plug detect x8 PCIe slot enabled using SW6 dip swi...

Page 64: ...ed to the System MAX10 FPGA Terasic had provided a board information IP that allow user can place it in the FPGA to read these board status Please refer to the section 5 4 for detailed Table 2 20 show...

Page 65: ...DE10 Agilex User Manual 65 www terasic com January 29 2021 INFO_SPI_MOSI Master output 1 2V PIN_CV17 INFO_SPI_CS_n Slave Select Master output 1 2V PIN_CR18...

Page 66: ...les generated include Quartus Prime Project File qpf Quartus Prime Setting File qsf Top Level Design File v External PLL Controller v Synopsis Design Constraints file sdc Pin Assignment Document htm T...

Page 67: ...plete the settings the System Builder will generate two major files which include top level design file v and the Quartus Prime setting file qsf The top level design file contains top level Verilog wr...

Page 68: ...e directory Tools SystemBuilder in the System CD Users can copy the entire folder to the host computer without installing the utility Please execute the SystemBuilder exe on the host computer as shown...

Page 69: ...ary 29 2021 Figure 3 3 Select FPGA Enter Project Name The project name entered in the circled area as shown in Figure 3 4 will be assigned automatically as the name of the top level design entry Figur...

Page 70: ...under System Configuration as shown in Figure 3 6 Each component of the FPGA board is listed to be enabled or disabled according to users needs If a component is enabled the System Builder will autom...

Page 71: ...et on DE10 Agilex can support single or dual rank DDR4 SO DIMM modules The FPGA control pins of these two DDR4 SO DIMM modules have some different such as clock enable pin or chip select pins see Figu...

Page 72: ...REFCLK QSFPDDRSV_REFCLK To use those clock users can select the desired frequency on the Si5340A0 groups as shown in Figure 3 9 QSFP DD port must be checked before users can start to specify the desir...

Page 73: ...emselves Figure 3 9 External programmable oscillators Project Setting Management The System Builder also provides functions to restore default DDR4 QDR II QDR IV setting load a pre saved setting and s...

Page 74: ...le 3 1 Files generated by the System Builder No Filename Description 1 Project name v or Project name vhdl Top Level Verilog VHDL File for Quartus Prime 2 si5340_controller Si5340A Clock Generator Con...

Page 75: ...VR_REF_312M5 4 h3 define XCVR_REF_250M 4 h4 define XCVR_REF_184M32 4 h5 define XCVR_REF_156M25 4 h6 define XCVR_REF_125M 4 h7 define XCVR_REF_100M 4 h8 wire si5340a_config_done wire si5340a_controller...

Page 76: ...get_ports CLK_50_B3A create_clock period 50 000000 MHz get_ports CLK_50_B3C create_clock period 50 000000 MHz get_ports UFL_CLKIN_p create_clock period 100 000000 MHz get_ports PCIE_REFCLK_p 0 create...

Page 77: ...les of user s project form host to the System MAX 10 FPGA through the JTAG interface Then the bit stream files will be written into the CFI Flash connected to the System MAX 10 FPGA via the PFL II IP...

Page 78: ...21 Figure 4 1 Block diagram of the Avalon ST x 16 mode on the board Note that the DE10 Agilex board ships with the CFI flash device preprogrammed with two FPGA configurations The two configuration ima...

Page 79: ...tion mode to AVSTx16 mode by setting SW6 and SW7 MSEL 2 0 as 101 as shown in Figure 4 2 and Figure 4 3 3 Specify the configuration of the FPGA using the default Factory Configuration Image or User Con...

Page 80: ...DE10 Agilex User Manual 80 www terasic com January 29 2021 Figure 4 2 Position of the MSEL 2 0 switch Figure 4 3 Set MSEL 2 0 to 110...

Page 81: ...w terasic com January 29 2021 Figure 4 4 Configuration Image Selection Figure 4 5 Position of the Configuration status LED 4 2 CFI Flash Memory Map The DE10 Agilex has one 1 Gbit 16 bit data width CFI...

Page 82: ...ory image and User image so the PLF II IP in the System MAX10 FPGA can know where to find the FPGA configuration data If developers erase all flash content please ensure that the PFL option is reprogr...

Page 83: ...ete the operations for the CFI Flash such as erasing and programming Users can find these batch files under the path System CD Demonstrations Flash_Restore Users can copy this Flash_Restore folder to...

Page 84: ...g file pfg will record the conversion settings for Programing File Generator and can be use in the command line The detailed description about the usage flow of these batch files is as follows Overrid...

Page 85: ...be automatically loaded into the FPGA for execution Erase When the users want to clear the design in CFI Flash they can execute Erase bat to complete this action 4 4 Restore Factory Settings This sect...

Page 86: ...s used to allow the user to confirm that the System MAX10 FPGA on the board can read the binary file from the Flash when the DE10 Agilex is power up and configure the Agilex FPGA through the AVSTx16 m...

Page 87: ...1 appropriate Avalon ST bus width In the DE10 Agilex Project please select AVST x 16 mode as shown in Figure 4 8 5 Click OK to confirm and close the Device and Pin Options dialog box Figure 4 7 Board...

Page 88: ...h the above Flash_Factory example code This project s FPGA configuration data and Nios II code are stored in the User hardware area See Table 4 1 when the FPGA board is shipped The major difference be...

Page 89: ...well as how to control the fan speed The source codes and tools of these examples are all available in the System CD 5 1 Configure Si5340A in RTL There is a Silicon Labs Si5340A clock generators on D...

Page 90: ...example in Demonstrations Clock_Controller folder This example shows how to instantiate the IP in Quartus top project Also System Builder tool located in System CD can be used to help developer to set...

Page 91: ...5340A Controller Instruction Ports Port Direction Description iCLK input System Clock 50Mhz iRST_n input Synchronous Reset 0 Module Reset 1 Normal iStart input Start to Configure positive edge trigger...

Page 92: ...the project For example in the components Si5340A change iXCVR_REFCLK_0 XCVR_REF_644M5312 to iXCVR_REFCLK_0 XCVR_REF_100M Recompile project the Si5340A OUT0 channel for QSFPDDB_REFCLK_p output freque...

Page 93: ...Own Frequency If the Si5340A control IP built in frequencies are not users desired users can refer to the below steps to the modify control IP register parameter settings to modify the IP to output a...

Page 94: ...Agilex User Manual 94 www terasic com January 29 2021 Figure 5 3 ClockBuilder Pro Wizard 2 After the installation select Si5340 and configure the input frequency and output frequency as shown in Figur...

Page 95: ...esign Report text which contains users setting frequency corresponding register value See Figure 5 5 Figure 5 5 Open Design Report on ClockBuilder Pro Wizard 4 Open Si5340 control IP sub module si5340...

Page 96: ...nstration shows how to use SI5340A Control IP written by Verilog to make si5340 clock generator to generate the desired frequency and using Quartus SignalTape II tool to verify whether the output freq...

Page 97: ...fQSFPDDA_REFCLK_p fQSFPDDB_REFCLK_p and fQSFPDDRSV_REFCLK_p The user can use the SignalTape II tool to observe the measurement registers in the module to verify whether the input frequency is correct...

Page 98: ...I result 5 3 Nios II control for SI5340 Temperature Power Fan This demonstration shows how to use the Nios II processor to program programmable clock generators Si5340A on the FPGA board how to measur...

Page 99: ...The Nios system will read these information or output the PLL control settings through PIO controllers Figure 5 10 Block diagram of the Nios II Basic Demonstration The system provides a menu in nios...

Page 100: ...tiplier and divider are embedded in it There is a sense resistor R4 0 003 for LTC2945 in the circuit when power on the Agilex Pro there will be a voltage drop named SENSE Voltage on R4 Based on sense...

Page 101: ...st bat test sh Demonstration Setup and Instructions Make sure Quartus Prime and Nios II are installed on your PC Power on the FPGA board Use the USB Cable to connect your PC and the FPGA board and ins...

Page 102: ...Agilex User Manual 102 www terasic com January 29 2021 Figure 5 12 Si5340A Demo For temperature power monitor and fan test please input key 1 and press Enter in the nios terminal as shown in Figure 5...

Page 103: ...x board provides several sensors to monitor the status of the board such as FPGA temperature board power monitor and fan speed status These interfaces are connected to the system MAX FPGA on the board...

Page 104: ...monstration SPI_Master SPI BOARD_INFO v Figure 5 15 shows the input and output pins of the board information IP Detailed pin descriptions and functions can be obtained from Table 5 4 Board information...

Page 105: ...signal for IP reset all logic MOSI Output 1 Master data output Please connect this signal to the INFO_SPI_MOSI pin MISO Input 1 Master data input Please connect this signal to the INFO_SPI_MISO pin C...

Page 106: ...of the second power channel Unit is mV CORE_Current2 Output 16 Current of the second power channel Unit is mA Fan_Speed Output 16 First fan speed of the board The unit of the output value is RPM Fan_S...

Page 107: ...he fan speed is abnormal this bit is 0 BIT6 Reserved to 0 BIT5 When shutdown occurs this bit is 0 BIT4 Reserved to 0 BIT3 LED_BOOT_PAGE enables the access to the flash memory device this bit is 0 BIT...

Page 108: ...8GB ECC SODIMM Module DDR4 SDRAM Test by Nios II Test four DDR4 2666 8GB ECC SODIMM Module with Nios II program 6 1 DDR4 SDRAM Test This demonstration performs a memory test function on the four DDR4...

Page 109: ...ODIMM please perform the two major steps below 1 Create correct pin assignments for the DDR4 SODIMM 2 Setup correct parameters in the dialog of the Agilex FPGA External Memory Interfaces Design Tools...

Page 110: ...hen LED stop blinking it means the test process is done In this case if the LED light it means the test result is passed If the LED is no light it means the test result is failed The LED0 represents t...

Page 111: ...p Memory The four 166 667MHz clock are used as reference clocks for the DDR4 controllers There are four DDR4 Controllers which are used in the demonstrations Each controller is responsible for one DDR...

Page 112: ...oject Compilation Before you attempt to compile the reference design under Nios II Eclipse make sure the project is cleaned first by clicking Clean from the Project menu of Nios II Eclipse Demonstrati...

Page 113: ...l as shown in Figure 6 3 and Figure 6 4 DDR4A and DDR4B test The program will display progressing and result information Press Button0 Button1 of the FPGA board to start SDRAM verify process and press...

Page 114: ...DE10 Agilex User Manual 114 www terasic com January 29 2021 Figure 6 4 Progress and Result Information for the DDR4B Test...

Page 115: ...DE10 Agilex User Manual 115 www terasic com January 29 2021 Figure 6 5 Progress and Result Information for the DDR4A DDR4D quick test...

Page 116: ...erface Agilex Hard IP for PCI Express with Avalon MM DMA IP is used in this demonstration For detail about this IP please refer to Intel document ug_ptile_pcie_avmm 7 1 PCI Express System Infrastructu...

Page 117: ...hich includes PCI Express Driver PCI Express Library PCI Express Examples The kernel mode driver assumes the PCIe vendor ID VID is 0x1172 and the device ID DID is 0x09C4 If different VID and DID are u...

Page 118: ...ws The PCIe library module TERASIC_PCIE_AVMM512 dll provides DMA and direct I O access allowing user application program to communicate with FPGA Users can develop their applications based on this DLL...

Page 119: ...tions PCIe_Fundamental demo_batch to configure the FPGA 4 Restart windows operation system 5 Click the Control Panel menu from Windows Start menu Click the Hardware and Sound item before clicking the...

Page 120: ...ck Browse my computer for driver software item as shown in Figure 7 4 Figure 7 4 Dialog of Browse my computer for the driver software 7 In the Browse for driver software on your computer dialog click...

Page 121: ...0 Agilex User Manual 121 www terasic com January 29 2021 Figure 7 5 Browse for the driver software on your computer 8 When the Windows Security dialog appears as shown Figure 7 6 click the Install but...

Page 122: ...l 122 www terasic com January 29 2021 Figure 7 6 Click Install in the dialog of Windows Security 9 When the driver is installed successfully the successfully dialog will appear as shown in Figure 7 7...

Page 123: ...January 29 2021 Figure 7 7 Click Close when the installation of the Altera PCI API Driver is complete 10 Once the driver is successfully installed users can see the Altera PCI API Driver under the de...

Page 124: ...M512 h TERASIC_PCIE_AVMM512 DLL 64 bit DLL Below lists the procedures to use the SDK files in users C C project 1 Create a 64 bit C C project 2 Include TERASIC_PCIE_AVMM512 h in the C C project 3 Copy...

Page 125: ...D uint8_t wCardIndex Parameters wVendorID Specify the desired vendor ID A zero value means to ignore the vendor ID wDeviceID Specify the desired device ID A zero value means to ignore the device ID wC...

Page 126: ...Read32 PCIE_HANDLE hPCIE PCIE_BAR PcieBar PCIE_ADDRESS PcieAddress uint32_t pdwData Parameters hPCIE A PCIe handle return by PCIE_Open function PcieBar Specify the target BAR PcieAddress Specify the t...

Page 127: ...FPGA board Return Value Return true if write data is successful otherwise false is returned PCIE_Read8 Function Read an 8 bit data from the FPGA board Prototype bool PCIE_Read8 PCIE_HANDLE hPCIE PCIE_...

Page 128: ...PcieBar Specify the target BAR PcieAddress Specify the target address in FPGA Byte Specify an 8 bit data which will be written to FPGA board Return Value Return true if write data is successful other...

Page 129: ...ata to the memory mapped memory of FPGA board in DMA Prototype bool PCIE_DmaWrite PCIE_HANDLE hPCIE PCIE_LOCAL_ADDRESS LocalAddress void pData uint64_t dwDataSize64 Parameters hPCIE A PCIe handle retu...

Page 130: ...ned 7 5 PCIe Reference Design Fundamental The application reference design shows how to implement fundamental control and data transfer in DMA In the design basic I O is used to control the BUTTON and...

Page 131: ...GA board installation on PC 2 Configure FPGA with DE10_Agilex sof by executing the test bat 3 Install the PCIe driver if necessary The driver is located in the folder CDROM Demonstration PCIe_SW_KIT W...

Page 132: ...DE10 Agilex User Manual 132 www terasic com January 29 2021 Figure 7 10 Screenshot for PCIe Driver 6 Go to windows_app folder execute PCIE_FUNDMENTAL exe A menu will appear as shown in Figure 7 11...

Page 133: ...c com January 29 2021 Figure 7 11 Screenshot of Program Menu 7 Type 0 followed by a ENTER key to select Led Control item then input 15 hex 0x0f will make all LEDs on as shown in Figure 7 12 If input 0...

Page 134: ...User Manual 134 www terasic com January 29 2021 Figure 7 12 Screenshot of LED Control 8 Type 1 followed by an ENTER key to select Button Status Read item The button status will be reported as shown in...

Page 135: ...Manual 135 www terasic com January 29 2021 Figure 7 13 Screenshot of Button Status Report 9 Type 2 followed by an ENTER key to select the DMA Testing item The DMA test result will be reported as show...

Page 136: ...ocation Quartus Project Demonstrations PCIe_Fundamental C Project Demonstrations PCIe_SW_KIT Windows PCIE_FUNDAMENTAL FPGA Application Design Figure 7 15 shows the system block diagram in the FPGA sys...

Page 137: ...ation software project is built by Visual C 2019 The project includes the following major files Name Description PCIE_FUNDAMENTAL cpp Main program PCIE c Implement dynamically load for TERAISC_PCIE_AV...

Page 138: ...en are defined in TERASIC_PCIE_AVMM512 h If developers change the Vendor ID and Device ID and PCI Express IP they also need to change the ID value defined in TERASIC_PCIE_AVMM512 h If the return value...

Page 139: ...PCIe_DDR4 demo_batch The folder includes following files FPGA Configuration File DE10_Agilex sof Download Batch file test bat Windows Application Software folder windows_app includes PCIE_DDR4 exe TER...

Page 140: ...rasic com January 29 2021 Figure 7 16 Screenshot of Program Menu 9 Type 2 followed by the ENTER key to select the Link Info item The PCIe link information will be shown as in Figure 7 17 Gen3 link spe...

Page 141: ...141 www terasic com January 29 2021 Figure 7 17 Screenshot of Link Info 10 Type 3 followed by the ENTER key to select DMA On Chip Memory Test item The DMA write and read test result will be reported...

Page 142: ...com January 29 2021 Figure 7 18 Screenshot of On Chip Memory DMA Test Result 11 Type 4 followed by the ENTER key to select the DMA DDR4 A SODIMM Memory Test item The DMA write and read test result wi...

Page 143: ...January 29 2021 Figure 7 19 Screenshot of the DDR4 A SOSIMM Memory DMA Test Result 12 Type 5 followed by the ENTER key to select the DMA DDR4 B SODIMM Memory Test item The DMA write and read test resu...

Page 144: ...om January 29 2021 Figure 7 20 Screenshot of the DDR4 B SOSIMM Memory DMA Test Result 13 Type 6 followed by an ENTER key to select DMA DDR4 C SODIMM Memory Test item The DMA write and read test result...

Page 145: ...January 29 2021 Figure 7 21 Screenshot of the DDR4 C SOSIMM Memory DMA Test Result 14 Type 7 followed by the ENTER key to select the DMA DDR4 D SODIMM Memory Test item The DMA write and read test resu...

Page 146: ...urce Code Location Quartus Project Demonstrations PCIE_DDR4 Visual C Project Demonstrations PCIe_SW_KIT Windows PCIe_DDR4 FPGA Application Design Figure 7 23 shows the system block diagram in the FPGA...

Page 147: ...he application software project is built by Visual C 2019 The project includes the following major files Name Description PCIE_DDR4 cpp Main program PCIE c Implement dynamically load for TERAISC_PCIE_...

Page 148: ...PCI Express driver The constant DEFAULT_PCIE_VID and DEFAULT_PCIE_DID used in the PCIE_Open are defined in TERASIC_PCIE_AVMM512 h If developers change the Vendor ID and Device ID and PCI Express IP th...

Page 149: ...www terasic com January 29 2021 The memory mapped memory read and write test is implemented by PCIE_DmaWrite and PCIE_DmaRead API as shown below The PCIe link information is implemented by PCIE_Confi...

Page 150: ...DE10 Agilex User Manual 150 www terasic com January 29 2021...

Page 151: ...face Agilex Hard IP for PCI Express with Avalon MM DMA IP is used in this demonstration For detail about this IP please refer to Intel document ug_ptile_pcie_avmm 8 1 PCI Express System Infrastructure...

Page 152: ...ibrary PCI Express Examples The kernel mode driver assumes the PCIe vendor ID VID is 0x1172 and the device ID DID is 0x09C4 If different VID and DID are used in the design users need to modify the PCI...

Page 153: ...pcie512_qsys so provides DMA and direct I O access for user application program to communicate with FPGA Users can develop their applications based on this so library file The intel_fpga_pcie_drv ko k...

Page 154: ...go to the folder CDROM Demonstrations PCIe_Fundamental demo_batch 4 Set QUARTUS_ROOTDIR variable pointing to the Quartus installation path Set QUARTUS_ROOTDIR variable by tying the following commands...

Page 155: ...ct 2 Include TERASIC_PCIE_AVMM512 h in the C C project 3 Copy terasic_pcie512_qsys so to the folder where the project execution file is located 4 Dynamically load terasic_pcie512_qsys so in C C progra...

Page 156: ...ard High speed data transfer is performed by the DMA Demonstration Files Location The demo file is located in the batch folder CDROM Demonstrations PCIe_Fundamental demo_batch The folder includes foll...

Page 157: ...et QUARTUS_ROOTDIR variable by tying the following commands in terminal Replace home user intelFPGA_pro 20 2 quartus to your quartus installation path export QUARTUS_ROOTDIR home user intelFPGA_pro 20...

Page 158: ...pp folder execute PCIE_FUNDAMENTAL A menu will appear as shown in Figure 8 5 Figure 8 5 Screenshot of Program Menu 9 Type 0 followed by the ENTER key to select the Led Control item then input 15 hex 0...

Page 159: ...ype 1 followed by the ENTER key to select the Button Status Read item The button status will be reported as shown in Figure 8 7 Figure 8 7 Screenshot of Button Status Report 11 Type 2 followed by the...

Page 160: ...tion Quartus Project Demonstrations PCIe_Fundamental C Project Demonstrations PCIe_SW_KIT Linux PCIE_FUNDAMENTAL FPGA Application Design Figure 8 9 shows the system block diagram in the FPGA system In...

Page 161: ...y GNU Toolchain The project includes the following major files Name Description PCIE_FUNDAMENTAL cpp Main program PCIE c Implement dynamically load for terasic_pcie512_qsys so library file PCIE h TERA...

Page 162: ...the Vendor ID and Device ID and PCI Express IP they also need to change the ID value defined in TERASIC_PCIE_AVMM512 h If the return value of PCIE_Open is zero it means the driver cannot be accessed...

Page 163: ...monstration Setup 1 Install four pieces of DDR4 2666 8GB SODIMM on the FPGA board 2 Make sure the SW7 DDR4A reference clock switch is set to FPGA OFF position 3 Install the FPGA board on the PCIe Slot...

Page 164: ...TER key to select the Link Info item The PCIe link information will be shown as in Figure 8 11 Gen3 link speed and x16 link width are expected Figure 8 11 Screenshot of Link Info 12 Type 3 followed by...

Page 165: ...t Result 13 Type 4 followed by the ENTER key to select the DMA DDR4 A SODIMM Memory Test item The DMA write and read test result will be reported as shown in Figure 8 13 Figure 8 13 Screenshot of DDR4...

Page 166: ...orted as shown in Figure 8 14 Figure 8 14 Screenshot of DDR4 B SOSIMM Memory DAM Test Result 15 Type 6 followed by the ENTER key to select the DMA DDR4 C SODIMM Memory Test item The DMA write and read...

Page 167: ...Tools Quartus Prime 20 2 Pro Edition GNU Compiler Collection Version 9 3 is recommended Demonstration Source Code Location Quartus Project Demonstrations PCIE_DDR4 C Project Demonstrations PCIe_SW_KIT...

Page 168: ...cation software project is built by GNU Toolchain The project includes the following major files Name Description PCIE_DDR4 cpp Main program PCIE c Implement dynamically load for terasic_pcie512_qsys...

Page 169: ...I Express driver The constant DEFAULT_PCIE_VID and DEFAULT_PCIE_DID used in the PCIE_Open are defined in TERASIC_PCIE_AVMM512 h If developers changes the Vendor ID and Device ID and PCI Express IP the...

Page 170: ...ww terasic com January 29 2021 The memory mapped memory read and write test is implemented via PCIE_DmaWrite and the PCIE_DmaRead API as shown below The PCIe link information is implemented by PCIE_Co...

Page 171: ...DE10 Agilex User Manual 171 www terasic com January 29 2021...

Page 172: ...tel Agilex devices are also provided For example Serial Lite IV IP CPRI PHY and 00G Ethernet Example are provides in the System CD 9 1 Transceiver Test Code The transceiver test code is used to verify...

Page 173: ...h two QSPF DD loopback fixtures installed Figure 9 2 QSPF DD Transceiver Loopback Test in Progress 9 3 Testing by Transceiver Test Code The transceiver test code is available in the folder System CD T...

Page 174: ...10 Agilex User Manual 174 www terasic com January 29 2021 Figure 9 3 The Transceiver PHY setting Figure 9 4 The Transceiver PHY setting The FPGA transceiver PMA setting used are shown in the table bel...

Page 175: ...QSPF DD loopback fixtures 4 Connect your FPGA board to your PC with a mini USB cable 5 Power on the FPGA board 6 Execute test bat in the Transceiver_Test folder under your local disk 7 The batch file...

Page 176: ...Agilex FPGA Design Example The E Tile Ethernet IP is used in the example design The IP is configured as 100GE MAC PC with 528 514 RS FEC This example executes the internal and external loopback test...

Page 177: ...elow Item Description Project Location alt_ehipc3_fm_100GE Quartus Project alt_ehipc3_fm_100GE hardware_test_design FPGA Bit Stream alt_ehipc3_fm_100GE demo_batch Test Scrip File alt_ehipc3_fm_100GE h...

Page 178: ...o QSFPDDA Channel 4 7 Yes No Yes QSFPDDB Channel 0 3 No Yes No QSFPDDB Channel 4 7 No Yes Yes Demonstration Setup Here is the procedure to setup the demonstration A QSFP28 or QSFPDD loopback fixtures...

Page 179: ...t and launch the System Console by selecting the menu item Tools System Debugging Tools System Console in Quartus 5 In the System Console window input the following commands to start the loopback test...

Page 180: ...DE10 Agilex User Manual 180 www terasic com January 29 2021 Figure 9 10 Launch the System Console for Ethernet 100G Demo...

Page 181: ...DE10 Agilex User Manual 181 www terasic com January 29 2021 Figure 9 11 Ethernet 100G loopback test report for RX Figure 9 12 Ethernet 100G loopback test report for TX...

Page 182: ...ht PAM4 lanes in a single link or 28 Gbps per lane with a maximum of 16 NRZ lanes This protocol offers high bandwidth low overhead frames low I O count and supports high scalability in both numbers of...

Page 183: ...red four transceivers as table below The pre compiled sof files for below four cases are available on the demo_batch folder Used Channel ENABLE_QSFPDDA ENABLE_QSFPDDA USE_CH_4567 QSFPDDA Channel 0 3 Y...

Page 184: ...er II driver is installed on the host PC 3 Go to the path Demonstration seriallite4_example_design demo_batch and chose a channel you want to test such as QSFPDDA_CH0123 see Figure 9 15 Execute test b...

Page 185: ...9 16 Terminal window for configuring FPGA Do not close this window 4 Open the Intel Quartus Prime Pro Edition software select Tools System Debugging Tools System Console to launch the system console S...

Page 186: ...ary 29 2021 Figure 9 18 System Console 5 As shown in Figure 9 19 click Load Design and select the sof file for the design example chose QSFPDDA_CH0123 folder in this example in the System Console Figu...

Page 187: ...the set JTAG master settings to enable communication between the development kit and toolkit Figure 9 20 Setup JTAG Master and Serial Lite IV IP 7 Please refer to the Figure 9 21 choose MAC and PCS ta...

Page 188: ...ab After Click Link initialization some link status messages will appear in the Message window at the bottom left corner This process will take a while please wait When the message PMA calibration don...

Page 189: ...x User Manual 189 www terasic com January 29 2021 Figure 9 22 Link initialization is done 8 Please refer to the Figure 9 23 choose GUI Configuration tab and follow steps 1 4 to set JTAG master for dem...

Page 190: ...Figure 9 24 choose Traffic statistics and bandwidth tab and follow steps 1 6 to implement various CSR for the Demo Management module to configure the traffic generator and checker Figure 9 25 shows th...

Page 191: ...DE10 Agilex User Manual 191 www terasic com January 29 2021 Figure 9 24 Traffic statistics and bandwidth tab Figure 9 25 Traffic statistics and bandwidth...

Page 192: ...192 www terasic com January 29 2021 10 If users enable the Continuously calculate effective bandwidth option as shown in Figure 9 26 it will show the real time bandwidth of this demonstration Figure 9...

Page 193: ...X10 FPGA on the DE10 Agilex through the UART interface and reads various status on the board See section 2 9 for detailed The reported status includes FPGA Board temperature fan speed FPGA core power...

Page 194: ...UART driver location Users can find it from the path Tool dashboard_gui Driver in the DE10 Agilex system CD and copy it to the Host Connection Setting 1 Connect the USB Mini USB connector of the DE10...

Page 195: ...com January 29 2021 Figure 10 3 Uninstalled USB to UART device Copy the device driver System CD Tool dashboard_gui Driver to the Host and install it as shown in Figure 10 4 Please note that the COM Po...

Page 196: ...device after driver is installed successfully 10 2 Run Dashboard GUI Dashboard GUI software location Users can find it from the path Tool dashboard_gui Dashboard exe in the DE10 Agilex system CD and...

Page 197: ...Figure 10 7 there is a Start button at the bottom left of the GUI window Click it to run the program Start will change to Stop it will show the DE10 Agilex board status Users can press Stop button to...

Page 198: ...A_SD_LED When this status is shown in green on the GUI it means that the FPGA temperature or the board temperature exceeds 95 degrees or the power consumption exceeds 180W All the power of the FPGA wi...

Page 199: ...real time show the DE10 Agilex board s ambient temperature Board and Board2 data in the GUI and FPGA and FPGA s transceiver E Tile and P Tile temperature Users can know the board s temperature status...

Page 200: ...DE10 Agilex User Manual 200 www terasic com January 29 2021 Figure 10 9 Temperature section Figure 10 10 Location of the board s ambient temperature...

Page 201: ...e 12V Power button See Figure 10 12 the GUI will display the voltage level and current number of 12V Power on the board While user clicking the FPGA Core Power button See Figure 10 13 the GUI will sho...

Page 202: ...re 10 15 If the FPGA power consumption is increasing due to the slight difference in PCB impedance of the two power channels the current of the two power channels may have a little difference instead...

Page 203: ...ilex User Manual 203 www terasic com January 29 2021 Figure 10 13 Select FPGA Monitor Section Figure 10 14 Two power channels of the FPGA core power Figure 10 15 One of the core power channel s curren...

Page 204: ...power channel s current is different Sampling Speed It can change interval time that the Dashboard GUI sample the board status Users can adjust it to 1s 10s 1min Full Speed 0 1s to sample the board st...

Page 205: ...and status export will appear Note that to active these functions you will need to stop obtaining the board status i e Don t Press Start button or Press Stop button in the GUI Detailed introductions o...

Page 206: ...the current MAX 10 FPGA software version and the DE10 Agilex board version as shown in Figure 10 20 Figure 10 20 Board Information Log File Click the Export in the File page to save the board tempera...

Page 207: ...DE10 Agilex User Manual 207 www terasic com January 29 2021 Figure 10 22 Export the log file in csv format...

Page 208: ...chnologies 9F No 176 Sec 2 Gongdao 5th Rd East Dist HsinChu City Taiwan 30070 Email support terasic com Web www terasic com DE10 Agilex Web DE10 Agilex terasic com Revision History Date Version Change...

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