Terasic Apollo Carrier Board Page 49 User Manual Download

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Apollo Carrier Board
User Manual

www.terasic.com

September 22, 2020

Figure 6-2

QSFP28 Loopback fixtures in the Apollo Develop kit

6.3

40G Ethernet Example

This 40G Ethernet example is generated according to the documents

Stratix 10 Low Latency 40G

Ethernet Design Example User Guide

. The Stratix 10 LL(Low Latency) 40GbE IP is used in the

example design. This example executes the external loopback test through one of the QSFP28

ports on the FPGA main board. A QSFP28 loopback fixture is required to perform this

demonstration.

Figure 6-3

shows the block diagram of this demonstration.

Summary of Contents for Apollo Carrier Board

Page 1: ...Apollo Carrier Board User Manual 1 www terasic com September 22 2020...

Page 2: ...CI Express 14 2 7 USB Downstream Port 15 Chapter 3 Board Assembly 17 3 1 SAMTEC JOM 17 3 2 Assembly 18 3 3 Disassembly 20 Chapter 4 Setup Thunderbolt 3 23 4 1 Hardware Requirement 23 4 2 Thunderbolt 3...

Page 3: ...pollo Carrier Board User Manual 2 www terasic com September 22 2020 6 1 Transceiver Test Code 47 6 2 QSFP28 Ports 47 6 3 40G Ethernet Example 48 Chapter 7 Additional Information 54 7 1 Getting Help 54...

Page 4: ...rd and installation guide 1 1 General Description Apollo Carrier board is a Carrier board design for Terasic Apollo S10 SoM board Apollo Carrier board and Apollo S10 SoM board communication via FMC an...

Page 5: ...als connect to S10 via FMC J1 and FMC connectors PCIe Gen3 x4 via Thunderbolt 3 Type C connector USB Downstream port via Thunderbolt 3 Type A connector Two QSFP28 connectors 40G Ethernet Clock generat...

Page 6: ...of the Apollo Carrier Board It depicts the layout of the board and indicates the location of the connectors and key components Users can refer to this figure for relative location of the connectors a...

Page 7: ...mbled please Always make Apollo S10 SoM power switch on Do not use the 2x4 PCIe power connector on Apollo S10 2 3 General User Input and Output This section describes the user I O interface of the Car...

Page 8: ...21 KEY 1 1 8 V C15 PIN_H21 2x20 GPIO Header Timing Expansion Header The board has one 2x20 GPIO headers The header has 36 user pins connected to the FMC connector via voltage level translator See Figu...

Page 9: ...lo Carrier Board User Manual 8 www terasic com September 22 2020 Figure 2 5 Location of the JP2 Table 2 2 Header setting for I O standard of the JP2 JP2 Setting FMC I O Standard 3 3V Default Setting 2...

Page 10: ...Apollo Carrier Board User Manual 9 www terasic com September 22 2020 1 8V Figure 2 6 Pin 1 of the GPIO header Figure 2 7 Pin out of 2x20 GPIO Header JP1...

Page 11: ...PIN_G22 FMC_GPIO_D 11 GPIO Connection 11 3 3 Default 2 5 1 8V C26 PIN_J23 FMC_GPIO_D 12 GPIO Connection 12 3 3 Default 2 5 1 8V D27 PIN_F22 FMC_GPIO_D 13 GPIO Connection 13 3 3 Default 2 5 1 8V D26 P...

Page 12: ...enable the clock generator developers must well control the control pins Si5340A_OE_n and Si5340A_RST_n on the Si5340A Figure 2 8 Si5340A of the Carrier Board Table 2 5 Clock Generator Pin Assignment...

Page 13: ...ignal Name Description I O Standard FMC Pin Num Apollo S10 FPGA Pin Num QSFP28A_INTERRUPT_n Interrupt 1 8 V H32 PIN_BF3 QSFP28A_LP_MODE Low Power Mode 1 8 V H31 PIN_BG3 QSFP28A_MOD_PRS_n Module Presen...

Page 14: ...H34 PIN_BJ3 QSFP28B_SCL 2 wire serial interface clock 1 8 V H35 PIN_BJ3 QSFP28B_SDA 2 wire serial interface data 1 8 V G33 PIN_BH3 QSFP28B_REFCLK_p QSFP28B transceiver reference clock p LVDS L4 PIN_T...

Page 15: ...Gbps lane and Gen3 at 8 0Gbps lane protocol stack solution compliant to PCI Express base specification 3 0 that includes PHY MAC data Link and transaction layer circuitry embedded in PCI Express hard...

Page 16: ...lo S10 board When the Apollo S10 module is connected to the carrier user can use a mini USB cable to connect the USB Blaster II circuit a mini USB connector on the Apollo S10 module and the USB downst...

Page 17: ...er Board User Manual 16 www terasic com September 22 2020 Figure 2 12 Connection setup for USB downstream port Carrier board to USB Blaster II Port Module board Figure 2 13 JTAG connection via USB dow...

Page 18: ...s shown in Figure 3 1 is used for board stacking Four JSOM standoff are required to assemble Apollo S10 SoM and Apollo Carrier Board Each JSOM standoff is consistent with four components The Apollo S1...

Page 19: ...Apollo S10 with carrier board to assemble the board 1 Use Philips Screwdriver and 5 0mm Hex Socket to screw four M2 5 Screws into four JSOM B on Apollo S10 as show in Figure 3 2 2 Use a Hex Key to sc...

Page 20: ...rrier Board User Manual 19 www terasic com September 22 2020 Figure 3 2 Assemble M2 5 Screws and JSOM B on Apollo S10 Figure 3 3 Assemble JSOM T to JSOM B Figure 3 4 Place Apollo Carrier Board over fo...

Page 21: ...semble with Apollo S10 SoM and Apollo Carrier Board or users can refer to the video How to disassemble Apollo S10 with carrier board to disassemble the board 1 Unscrew four Hex Nut as shown in Figure...

Page 22: ...Apollo Carrier Board User Manual 21 www terasic com September 22 2020 Figure 3 7 Disassemble Hex Nut Figure 3 8 Disassemble JSOM T to JSOM B...

Page 23: ...Apollo Carrier Board User Manual 22 www terasic com September 22 2020 Figure 3 9 Unscrew JSOM B...

Page 24: ...ion for the FPGA and the Host PC via a Thunderbolt 3 cable Therefore a Host PC equipment with Thunderbolt 3 port is required to work with the Apollo Developer Kit for PCIe applications This chapter wi...

Page 25: ...olt 3 Cable 4 2 Thunderbolt 3 Test on Windows OS Below shows the procedure when the Apollo Developer Kit is first time to plug into the Thunderbolt 3 port of the Host PC 1 Make sure your Host PC had i...

Page 26: ...of your screen as shown in Figure 4 4 Click the message to approve the device Figure 4 4 New Thunderbolt devices have been attached message Note that if this message does not appear user can reconnec...

Page 27: ...FPGA then re establish the Thunderbolt 3 connection to the Host that allow the Host to detect the PCIe device in the FPGA Below we introduce the use of a Terasic PCIe demo to demonstrate the detectio...

Page 28: ...erbolt connection setting as described in the section 4 2 7 Open the Device Manager in the Win10 you may see an unknown PCI Device See Figure 4 6 that means the PCIe design is detected by the Host via...

Page 29: ...detail about this IP please refer to Intel document ug_s10_pcie_avmm pdf Note before user start to use the PCIe design with the Apollo Develop kit please refer to the section 4 3 to setup Thunderbolt...

Page 30: ...he PCI Express Library is implemented as a single DLL named TERASIC_PCIE_AVMM DLL This file is a 64 bit DLL When the DLL is exported to the software API users can easily communicate with the FPGA The...

Page 31: ...xecute the steps below 1 Connect the Apollo develop kit and the Host PC with Thunderbolt 3 cable 2 Make sure the Intel Quartus Programmer and USB Blaster II driver are installed 3 Execute test bat in...

Page 32: ...lect the Updated Driver Software items Figure 5 3 Screenshot of launching Update Driver Software dialog 6 In the How do you want to search for the driver software dialog click Browse my computer for d...

Page 33: ...driver inf is located as shown in Figure 5 5 Click the Next button Figure 5 5 Browse for the driver software on your computer 8 When the Windows Security dialog appears as shown Figure 5 6 click the I...

Page 34: ...ure 5 7 Click Close when the installation of the Altera PCI API Driver is complete 10 Once the driver is successfully installed users can see the Altera PCI API Driver under the device manager window...

Page 35: ...Call the SDK API to implement the desired application Users can easily communicate with the FPGA through the PCIe bus through the TERASIC_PCIE_AVMM DLL API The details of API are described below 5 4...

Page 36: ...andle once the handle is no longer used PCIE_Close Function Close a handle associated to the PCIe card Prototype void PCIE_Close PCIE_HANDLE hPCIE Parameters hPCIE A PCIe handle return by PCIE_Open fu...

Page 37: ...e handle return by PCIE_Open function PcieBar Specify the target BAR PcieAddress Specify the target address in FPGA dwData Specify a 32 bit data which will be written to FPGA board Return Value Return...

Page 38: ..._ADDRESS PcieAddress uint8_t Byte Parameters hPCIE A PCIe handle return by PCIE_Open function PcieBar Specify the target BAR PcieAddress Specify the target address in FPGA Byte Specify an 8 bit data w...

Page 39: ...nction Write data to the memory mapped memory of FPGA board in DMA Prototype bool PCIE_DmaWrite PCIE_HANDLE hPCIE PCIE_LOCAL_ADDRESS LocalAddress void pData uint32_t dwDataSize Parameters hPCIE A PCIe...

Page 40: ...s Location The demo file is located in the batch folder CDROM Demonstrations PCIe_DDR4 demo_batch The folder includes following files FPGA Configuration File S10C_top sof Download Batch file test bat...

Page 41: ...xe A menu will appear as shown in Figure 5 10 Figure 5 10 Screenshot of Program Menu 8 Type 0 or 1 can control the LED ON OFF or read the status of the button of the Apollo develop kit 9 Type 2 follow...

Page 42: ...R key to select DMA On Chip Memory Test item The DMA write and read test result will be reported as shown in Figure 5 12 Figure 5 12 Screenshot of On Chip Memory DMA Test Result 11 Type 4 followed by...

Page 43: ...c com September 22 2020 Figure 5 13 Screenshot of the DDR4A Bank Memory DMA Test Result 12 Type 5 followed by the ENTER key to select the DMA DDR4B bank Memory Test item The DMA write and read test re...

Page 44: ...DDR4B Bank Memory DMA Test Result 13 Type 99 followed by the ENTER key to exit this test program Development Tools Quartus Prime 19 1 Pro Edition Visual C 2012 Demonstration Source Code Location Quar...

Page 45: ...CI Express Hard IP controller through the Memory Mapped Interface Figure 5 15 Hardware block diagram of the PCIe_DDR4 reference design Windows Based Application Software Design The application softwar...

Page 46: ...and DEFAULT_PCIE_DID used in the PCIE_Open are defined in TERASIC_PCIE_AVMM h If developers change the Vendor ID and Device ID and PCI Express IP they also need to change the ID value defined in TERA...

Page 47: ...Apollo Carrier Board User Manual 46 www terasic com September 22 2020 The PCIe link information is implemented by PCIE_ConfigRead32 API as shown below...

Page 48: ...e transceiver test code is used to verify the transceiver channels via the QSPF28 ports through an external loopback method The transceiver channels are verified with the data rates 10 3125 Gbps for t...

Page 49: ...ated according to the documents Stratix 10 Low Latency 40G Ethernet Design Example User Guide The Stratix 10 LL Low Latency 40GbE IP is used in the example design This example executes the external lo...

Page 50: ...h Test Scrip File CDROM Demonstrations alt_e40 hardware_test_design hwtest main tcl Quartus Version Quartus Prime 19 4 Pro Edition Demonstration Setup Here is the procedure to setup the demonstration...

Page 51: ...ter II driver is installed on the Host PC 4 Make sure the USB Blaster II is detected correctly 5 Go to the path System_CD Demonstration alt_e40 demo_batch Execute the batch file test bat to program th...

Page 52: ...September 22 2020 Figure 6 5 Launch the System Console for Ethernet 40G Demo 6 If you have a QSFP28 loopback fixture installed type loop_off to turns off internal serial loopback Otherwise type loop_o...

Page 53: ...r Manual 52 www terasic com September 22 2020 Figure 6 6 Enter command for test 7 Type start_pkt_gen to starts the packet generator 8 Type chkmac_stats to display the values in the MAC statics counter...

Page 54: ...Apollo Carrier Board User Manual 53 www terasic com September 22 2020 Figure 6 7 Ethernet 40G loopback test report for RX and TX...

Page 55: ...problems Terasic Technologies 9F No 176 Sec 2 Gongdao 5th Rd East Dist HsinChu City Taiwan 30070 Email support terasic com Web www terasic com Revision History Date Version Changes 2020 04 First publi...

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