TENX TECHNOLOGY 82314BW User Manual Download Page 1

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TM59PA80

8 bit

Microcontroller

tenx technology, inc.

Rev 1.2, 2007/03/06

TM59PA80

User’s Manual

tenx technology, inc.

Summary of Contents for 82314BW

Page 1: ...TM59PA80 8 bit Microcontroller 0 tenx technology inc Rev 1 2 2007 03 06 TM59PA80 User s Manual tenx technology inc ...

Page 2: ...e 11 1 4 ALU and Working W Register 12 1 5 STATUS Register 13 1 6 Interrupt 13 1 7 Reset 14 1 8 Power Down Mode 15 1 9 Instruction Set 15 2 Control Registers 29 3 8 Bit Timer 61 4 8 Bit PWM 65 5 Analog to Digital Converter 67 6 I O Ports 69 7 LCD Controller 75 8 Buzzer Out 80 9 Serial I O 82 10 Electrical Characteristics 86 11 Packaging Information 92 ...

Page 3: ...ns at 12 MHz fSYS minimum 5 Interrupts 15 interrupt sources with one vector one level 6 I O Ports Total 36 bit programmable pins 44QFP Total 34 bit programmable pins 42SDIP 7 Timers Two 8 bit timer counter Interval mode Timer0 1 Configurable as one 16 bit timer counter One Real time and interval time measurement Timer2 8 PWM 8 bit PWM 1 ch 6 bit base 2 bit extension 9 Watchdog Timer 221 oscillator...

Page 4: ...t receive mode LSB first or MSB first transmission selectable Internal or external clock source 14 Low Voltage Detector LVD Voltage level detection Low Voltage Check to make system reset LVR VLVD 2 3V 3 0V 3 9V 15 Operating Temperature Range 40 C to 85 C 16 Operating Voltage Range 2 0 V to 5 5 V at 0 4 4 2 MHz 2 5 V to 5 5 V at 0 4 12 MHz 17 Package Type 44 pin QFP 44 pin LQFP 42 pin SDIP 40 pin D...

Page 5: ...ram Memory 192 Byte SRAM Port A CORE Port B 10 bit ADC 6 ch 8 bit Timer0 WDT Timer OSC External RC Port I O Interrupt Control 20 Byte LCD Buffer 8 bit Timer1 8 bit Timer2 SIO LCD Controller Port C Port G Port F Port E Port D Buzzer Out 8 bit PWM Figure 1 1 Block Diagram ...

Page 6: ...UM TM59PA80_E 5 tenx technology inc Rev 1 2 2007 03 06 Figure 1 2 Pin Assignment Diagram 44 Pin QFP Package ...

Page 7: ...UM TM59PA80_E 6 tenx technology inc Rev 1 2 2007 03 06 Figure 1 3 Pin Assignment Diagram 44 Pin LQFP Package ...

Page 8: ... 3 AD0 INT4 PB 0 AD1 INT5 PB 1 AD2 INT6 PB 2 AD3 INT7 PB 3 VDD VSS XOUT XIN nTEST XTIN XTOUT nRESET PWM0 PC 3 SI PC 2 SO SEG0 PC 1 SCLK SEG1 PC 0 PG 2 COM1 PG 1 COM2 PG 0 COM3 PF 7 COM4 SEG19 PF 6 COM5 SEG18 PF 5 COM6 SEG17 PF 4 COM7 SEG16 PF 3 SEG15 PF 2 SEG14 PF 1 SEG13 PF 0 SEG12 PE 7 SEG11 PE 6 SEG10 PE 5 SEG9 PE 4 SEG8 PE 3 SEG7 PE 2 SEG6 PE 1 SEG5 PE 0 SEG4 PD 0 SEG3 INT9 PD 1 SEG2 INT8 Figu...

Page 9: ...UM TM59PA80_E 8 tenx technology inc Rev 1 2 2007 03 06 Figure 1 5 Pin Assignment Diagram 40 Pin DIP Package ...

Page 10: ...rrupt 4 7 ADC0 3 INT4 7 PC 0 PC 3 I O Schmitt trigger input Push pull output Open Drain output SEG0 1 SCLK SO SI PWM0 SCLK SO SEG0 1 SI PWM0 PD 0 PD 1 I O Schmitt trigger input Push pull output Open Drain output External Interrupt 8 9 SEG2 3 INT8 9 SEG2 3 PE 0 PE 7 I O Schmitt trigger Input Push pull output Open Drain output SEG4 11 Input mode with pull up SEG4 11 PF 0 PF 7 I O Schmitt trigger Inp...

Page 11: ...un by setting OSCCON 2 Idle mode control is described in section in 1 8 Power Down mode 2 SYSTEM CLOCK CONTROL REGISTER CLKCON The system clock control register CLKCON has the following functions Oscillator frequency divider After a reset the main oscillator is activated and the fSYS 16 the slowest clock speed is selected as the CPU clock If necessary you can then increase the CPU clock speed to f...

Page 12: ...cles since the fetch instruction is flushed from the pipeline while the new instruction is being fetched and then executed 1 3 Addressing Mode The Programming Counter is 13 bit wide capable of addressing a 8K x 14 program ROM As a program instruction is executed the PC will contain the address of the next program instruction to be executed The PC value is normally increased by one except the follo...

Page 13: ...will produce 00h Writing to the INDF register indirectly results in a no operation Program Memory 0000 Reset Vector 0001 Interrupt Vector 0FFF Program ROM Page0 1000 1FFF Program ROM Page1 Figure 1 7 Address space 1 4 ALU and Working W Register The ALU is 8 bits wide and capable of addition subtraction shift and logical operations In two operand instructions typically one operand is the W register...

Page 14: ...ources Each interrupt source has its own enable control bit An interrupt event will set its individual flag Because TM59PA80 has only 1 vector there is not a interrupt priority register The interrupt priority is determined by F W Interrupt Vector Interrupt Pending i Flag Interrupt Enable Interrupt Source Figure 1 8 Interrupt Function Diagram If the corresponding interrupt enable bit has been set i...

Page 15: ...t High level if the signal at the nRESET pin is forced Low then the reset operation starts All system and peripheral control registers are then set to their default hardware reset values The Low Voltage Reset features static reset when supply voltage is below a reference value LVDCON is used to select reference voltage LVD enable control reset enable control and check voltage level status The Watc...

Page 16: ...nstruction type and one or more operands which further specify the operation of the instruction The instructions can be categorized as byte oriented bit oriented and literal operations list in the following table For byte oriented instructions f represents address designator and d represents destination designator The address designator is used to specify which address in Program memory is to be u...

Page 17: ...f 1 Swap nibble of f TESTZ f 00 1000 1fff ffff 1 Z Test if f is zero XORWF f d 00 0110 dfff ffff 1 Z XOR W with f Bit Oriented File Register Instruction BCF f b 01 000b bbff ffff 1 Clear b bit of f BSF f b 01 001b bbff ffff 1 Set b bit of f BTFSC f b 01 010b bbff ffff 1 or 2 Test b bit of f skip if clear BTFSS f b 01 011b bbff ffff 1 or 2 Test b bit of f skip if set Literal and Control Instruction...

Page 18: ... d 0 1 Operation Destination W f Status Affected C DC Z OP Code 00 0111 dfff ffff Description Add the contents of the W register with register f If d is 0 the result is stored in the W register If d is 1 the result is stored back in register f Cycle 1 Example ADDWF FSR 0 B W 0x17 FSR 0xC2 A W 0xD9 FSR 0xC2 ANDLW Logical AND Literal k with W Syntax ANDLW k Operands k 00h FFh Operation W W AND f Sta...

Page 19: ... in register f Cycle 1 Example ANDWF FSR 1 B W 0x17 FSR 0xC2 A W 0x17 FSR 0x02 BCF Clear b bit of f Syntax BCF f b Operands f 00h 3Fh b 0 7 Operation f b 0 Status Affected OP Code 01 000b bbff ffff Description Bit b in register f is cleared Cycle 1 Example BCF FLAG_REG 7 B FLAG_REG 0xC7 A FLAG_REG 0x47 BSF Set b bit of f Syntax BCF f b Operands f 00h 3Fh b 0 7 Operation f b 1 Status Affected OP Co...

Page 20: ...erands f 00h 3Fh b 0 7 Operation Skip next instruction if f b 1 Status Affected OP Code 01 011b bbff ffff Description If bit b in register f is 0 then the next instruction is executed If bit b in register f is 1 then the next instruction is discarded and a NOP is executed instead making this a 2nd cycle instruction Cycle Example LABEL1 BTFSS FLAG 1 TRUE GOTO SUB1 FALSE B PC LABEL1 A if FLAG 1 0 PC...

Page 21: ...B FLAG_REG 0x5A A FLAG_REG 0x00 Z 1 CLRW Clear W Syntax CLRW Operands Operation W 00h Z 1 Status Affected Z OP Code 00 0001 0100 0000 Description W register is cleared and Zero bit Z is set Cycle 1 Example CLRW B W 0x5A A W 0x00 Z 1 CLRWDT Clear Watchdog Timer Syntax CLRWDT Operands Operation WDTE 00h Status Affected OP Code 00 0000 0000 0100 Description CLRWDT instruction enables and resets the W...

Page 22: ... If d is 0 the result is stored in the W register If d is 1 the result is stored back in register f Cycle 1 Example DECF CNT 1 B CNT 0x01 Z 0 A CNT 0x00 Z 1 DECFSZ Decrement f Skip if 0 Syntax DECFSZ f d Operands f 00h 7Fh d 0 1 Operation destination f 1 skip next instruction if result is 0 Status Affected OP Code 00 1011 dfff ffff Description The contents of register f are decremented If d is 0 t...

Page 23: ... If d is 0 the result is placed in the W register If d is 1 the result is placed back in register f Cycle 1 Example INCF CNT 1 B CNT 0xFF Z 0 A CNT 0x00 Z 1 INCFSZ Increment f Skip if 0 Syntax INCFSZ f d Operands f 00h 7Fh d 0 1 Operation destination f 1 skip next instruction if result is 0 Status Affected OP Code 00 1111 dfff ffff Description The contents of register f are incremented If d is 0 t...

Page 24: ...ive OR W with f Syntax IORWF f d Operands f 00h 7Fh d 0 1 Operation destination W OR k Status Affected Z OP Code 00 0100 dfff ffff Description Inclusive OR the W register with register f If d is 0 the result is placed in the W register If d is 1 the result is placed back in register f Cycle 1 Example IORWF RESULT 0 B RESULT 0x13 W 0x91 A RESULT 0x13 W 0x93 Z 0 MOVFW Move f to W Syntax MOVFW f Oper...

Page 25: ... cares will as semble as 0 s Cycle 1 Example MOVLW 0x5A B W A W 0x5A MOVWF Move W to f Syntax MOVWF f Operands f 00h 7Fh Operation f W Status Affected OP Code 00 0000 1fff ffff Description Move data from W register to register f Cycle 1 Example MOVWF REG1 B REG1 0xFF W 0x4F A REG1 0x4F W 0x4F NOP No Operation Syntax NOP Operands Operation No Operation Status Affected Z OP Code 00 0000 0000 0000 De...

Page 26: ...h Operation PC TOS W k Status Affected OP Code 01 1000 kkkk kkkk Description The W register is loaded with the eight bit literal k The program counter is loaded from the top of the stack the return address This is a two cycle instruction Cycle 2 Example CALL TABLE TABLE ADDWF PCL RETLW k1 RETLW k2 RETLW kn B W 0x07 A W value of k8 RET Return from Subroutine Syntax RET Operands Operation PC TOS Sta...

Page 27: ...W 1100 1100 C 1 RRF Rotate Right f through Carry Syntax RRF f d Operands f 00h 7Fh d 0 1 Operation C Register f Status Affected C OP Code 00 1100 dfff ffff Description The contents of register f are rotated one bit to the right through the Carry Flag If d is 0 the result is placed in the W register If d is 1 the result is placed back in register f Cycle 1 Example RRF REG1 0 B REG1 1110 0110 C 0 A ...

Page 28: ...0 W 2 C 1 Z 1 B REG1 1 W 2 C Z A REG1 FFh W 2 C 0 Z 0 SWAPF Swap Nibbles in f Syntax SWAPF f d Operands f 00h 7Fh d 0 1 Operation destination 7 4 f 3 0 destination 3 0 f 7 4 Status Affected OP Code 00 1110 dfff ffff Description The upper and lower nibbles of register f are exchanged If d is 0 the result is placed in W register If d is 1 the result is placed in register f Cycle 1 Example SWAPF REG ...

Page 29: ...al k The result is placed in the W register Cycle 1 Example XORLW 0xAF B W 0xB5 A W 0x1A XORWF Exclusive OR W with f Syntax XORWF f d Operands f 00h 7Fh d 0 1 Operation destination W XOR f Status Affected Z OP Code 00 0110 dfff ffff Description Exclusive OR the contents of the W register with register f If d is 0 the result is stored in the W register If d is 1 the result is stored back in registe...

Page 30: ...ONH 07 PCD PAPU PFCONL 08 PDD PBCON PFCONH 09 WDTE 0A PWRDN 0B PED PBPU PGCON 0C PFD PCCON PWM0CON 0D PGD PCPU PWM0DAT 0E T0CON PDCON LCDCON 0F T0DATA PINTD0 LPCON 10 T1CON PINTD1 LVDCON 11 T1DATA PINTD2 ADCDATL 12 T2CON INTCON0 ADCDATH 13 BZCON INTCON1 SIOPS 14 ADCCON 15 SIOCON STOPCON 16 SIODAT 17 INTPND0 18 INTPND1 19 SYSTEM Use Only 1A GPR0 1B GPR1 1C GPR2 1D GPR3 1E GPR4 1F GPR5 ...

Page 31: ...DC4 PA 4 1 0 1 ADC5 PA 5 Others Not Used 3 End of Conversion Status Bit 0 A D conversion is in progress 1 A D conversion complete 2 1 Clock Source Selection Bit 0 0 fSYS 16 fSYS 10 MHz 0 1 fSYS 8 fSYS 10 MHz 1 0 fSYS 4 fSYS 10 MHz 1 1 fSYS 1 fSYS 4 MHz 0 Conversion Start Bit 0 Disable Operation 1 A D conversion start Auto clear Maximum ADC Input Clock is 4MHz ADCDATL ADC Data Register Low Byte Ban...

Page 32: ...ster Bank0 13H Bit 7 6 5 4 3 2 1 0 Related Register Reset Value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W Bit Description 7 6 Input Clock Selection 0 0 fSYS 8 0 1 fSYS 16 1 0 fSYS 32 1 1 fSYS 64 5 0 Buzzer Period Data XXXXXX Period Data CLKCON Clock Control Register Bank1 01H Bit 7 6 5 4 3 2 1 0 See Also Reset Value 0 0 R W R W R W Bit Description 7 2 Not Used 1 0 Divided by Selection Bi...

Page 33: ...d 6 0 File Select Register 000 0000 Not Used 1 7Fh Indirect Addressing Location GPR0 5 General Purpose Register 1AH 1FH Bit 7 6 5 4 3 2 1 0 Related Register Reset Value R W R W R W R W R W R W R W R W R W Bit Description 7 0 General Purpose Register GPR0 5 are mirrored all bank It is useful to pass arguments to SUB routine or backup Working register W and STAT register in ISR or SUB routine ...

Page 34: ...ption 7 EXTINT7 Interrupt Enable Bit 0 Disable 1 Enable 6 EXTINT6 Interrupt Enable Bit 0 Disable 1 Enable 5 EXTINT5 Interrupt Enable Bit 0 Disable 1 Enable 4 EXTINT4 Interrupt Enable Bit 0 Disable 1 Enable 3 EXTINT3 Interrupt Enable Bit 0 Disable 1 Enable 2 EXTINT2 Interrupt Enable Bit 0 Disable 1 Enable 1 EXTINT1 Interrupt Enable Bit 0 Disable 1 Enable 0 EXTINT0 Interrupt Enable Bit 0 Disable 1 E...

Page 35: ...R W Bit Description 7 PWM0 Interrupt Enable Bit 0 Disable 1 Enable 6 Timer 2 Interrupt Enable Bit 0 Disable 1 Enable 5 Timer 1 Match Interrupt Enable Bit 0 Disable 1 Enable 4 Timer 0 Match Interrupt Enable Bit 0 Disable 1 Enable 3 Not Used 2 SIO Interrupt Enable Bit 0 Disable 1 Enable 1 EXTINT9 Interrupt Enable Bit 0 Disable 1 Enable 0 EXTINT8 Interrupt Enable Bit 0 Disable 1 Enable ...

Page 36: ...ending read Pending bit clear write 1 Interrupt is pending read No effect write 4 EXTINT4 Interrupt Pending Bit 0 No interrupt pending read Pending bit clear write 1 Interrupt is pending read No effect write 3 EXTINT3 Interrupt Pending Bit 0 No interrupt pending read Pending bit clear write 1 Interrupt is pending read No effect write 2 EXTINT2 Interrupt Pending Bit 0 No interrupt pending read Pend...

Page 37: ...ct write 5 Timer 1 Match Interrupt Pending Bit 0 No interrupt pending read Pending bit clear write 1 Interrupt is pending read No effect write 4 Timer 0 Match Interrupt Pending Bit 0 No interrupt pending read Pending bit clear write 1 Interrupt is pending read No effect write 3 Not Used 2 SIO Interrupt Pending Bit 0 No interrupt pending read Pending bit clear write 1 Interrupt is pending read No e...

Page 38: ...0 Display Off Cut Off the LCD Voltage dividing resistors 1 Display On 3 2 LCD Duty and Bias Selection Bit 0 0 1 3 duty 1 3 bias COM0 COM2 SEG0 SEG19 0 1 1 4 duty 1 3 bias COM0 COM3 SEG0 SEG19 1 0 1 8 duty 1 4 bias COM0 COM7 SEG0 SEG15 1 1 1 8 duty 1 5 bias COM0 COM7 SEG0 SEG15 1 0 LCD Clock Selection Bits 0 0 fT2 27 256 Hz fT2 32 768 Hz 0 1 fT2 26 512 Hz fT2 32 768 Hz 1 0 fT2 25 1024 Hz fT2 32 768...

Page 39: ...it 0 0 0 PE 0 PG 3 I O 0 0 1 PE 0 PF 7 I O PG 0 PG 3 LCD Signal 0 1 0 PE 0 PF 3 I O PF 4 PG 3 LCD Signal 0 1 1 PE 0 PE 7 I O PF 0 PG 3 LCD Signal 1 0 0 PE 0 PE 3 I O PE 4 PG 3 LCD Signal 1 0 1 PE 0 PG 3 LCD Signal Others Not Used 3 SEG3 PORTD 0 Selection Bit 0 Normal I O 1 SEG Enable 2 SEG2 PORTD 1 Selection Bit 0 Normal I O 1 SEG Enable 1 SEG1 PORTC 0 Selection Bit 0 Normal I O 1 SEG Enable 0 SEG...

Page 40: ...W R W R W R W R W Bit Description 7 Low Voltage Detector Enable Bit 0 Disable Low Voltage Detector 1 Enable Low Voltage Detector 6 RESET Enable Bit 0 Disable Reset 1 Enable Reset 5 Voltage Level Status Bit 0 VDD is lower than reference voltage 1 VDD is higher than reference voltage 4 0 Reference Voltage Selection Bit 11011 2 3V 10000 3 0V 01110 3 9V Others Not Used ...

Page 41: ...ption 7 4 Not Used 4 Clock Switching Status Bit 0 Switched to Main oscillator 1 Switched to Sub oscillator 3 Main Oscillator Control Bit 0 Main oscillator RUN 1 Main oscillator STOP 2 Sub Oscillator Control Bit 0 Sub oscillator RUN 1 Sub oscillator STOP 1 System Clock Selection Bit 0 Main oscillator select 1 Sub oscillator select 0 Idle Mode Control Bit 0 No Effect 1 Enter Idle Mode ...

Page 42: ...s than PC PACONL Port A Control Register Low Byte Bank1 05H Bit 7 6 5 4 3 2 1 0 See Also Reset Value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit Description 7 6 Port A 3 Configuration Bits 0 0 Schmitt trigger Input INT3 0 1 Push pull output 1 0 Open drain output 1 1 Buzzer Out 5 4 Port A 2 Configuration Bits 0 0 Schmitt trigger Input INT2 0 1 Push pull output 1 0 Open drain output 1 1 ...

Page 43: ...Used 3 2 Port A 5 Configuration Bits 0 0 Schmitt trigger Input 0 1 Push pull output 1 0 Open drain output 1 1 ADC5 1 0 Port A 4 Configuration Bits 0 0 Schmitt trigger Input 0 1 Push pull output 1 0 Open drain output 1 1 ADC4 PAD Port A Data Register Bank0 05H Bit 7 6 5 4 3 2 1 0 Related Register Reset Value 0 0 0 0 0 0 R W R W R W R W R W R W R W Bit Description 7 6 Not Used 5 0 Port A 5 0 Data Bi...

Page 44: ...7 6 Not Used 5 Port A 5 Pull up Enable Bit 0 Pull up Disable 1 Pull up Enable 4 Port A 4 Pull up Enable Bit 0 Pull up Disable 1 Pull up Enable 3 Port A 3 Pull up Enable Bit 0 Pull up Disable 1 Pull up Enable 2 Port A 2 Pull up Enable Bit 0 Pull up Disable 1 Pull up Enable 1 Port A 1 Pull up Enable Bit 0 Pull up Disable 1 Pull up Enable 0 Port A 0 Pull up Enable Bit 0 Pull up Disable 1 Pull up Enab...

Page 45: ... Bits 0 0 Schmitt trigger Input INT7 0 1 Push pull output 1 0 Open drain Output 1 1 ADC3 5 4 Port B 2 Configuration Bits 0 0 Schmitt trigger Input INT6 0 1 Push pull output 1 0 Open drain Output 1 1 ADC2 3 2 Port B 1 Configuration Bits 0 0 Schmitt trigger Input INT5 0 1 Push pull output 1 0 Open drain Output 1 1 ADC1 1 0 Port B 0 Configuration Bits 0 0 Schmitt trigger Input INT4 0 1 Push pull outp...

Page 46: ...Data Bits PBPU Port B Pull Up Control Register Bank1 0BH Bit 7 6 5 4 3 2 1 0 See Also Reset Value 0 0 0 0 R W R W R W R W R W Bit Description 7 4 Not Used 3 Port B 3 Pull up Enable Bit 0 Pull up Disable 1 Pull up Enable 2 Port B 2 Pull up Enable Bit 0 Pull up Disable 1 Pull up Enable 1 Port B 1 Pull up Enable Bit 0 Pull up Disable 1 Pull up Enable 0 Port B 0 Pull up Enable Bit 0 Pull up Disable 1 ...

Page 47: ...1 PWM Out 5 4 Port C 2 Configuration Bits 0 0 Schmitt trigger Input SI 0 1 Push pull output 1 X Open drain Output 3 2 Port C 1 Configuration Bits 0 0 Schmitt trigger Input 0 1 Push pull output 1 0 Open drain Output 1 1 SO 1 0 Port C 0 Configuration Bits 0 0 Schmitt trigger Input SCLK In 0 1 Push pull output 1 0 Open drain Output 1 1 SCLK Out PCD Port C Data Register Bank0 07H Bit 7 6 5 4 3 2 1 0 R...

Page 48: ... Port C 1 Pull up Enable Bit 0 Pull up Disable 1 Pull up Enable 0 Port C 0 Pull up Enable Bit 0 Pull up Disable 1 Pull up Enable PDCON Port D Control Register Bank1 0EH Bit 7 6 5 4 3 2 1 0 See Also Reset Value 0 0 0 0 R W R W R W R W R W Bit Description 7 4 Not Used 3 2 Port D 1 Configuration Bits 0 0 Schmitt trigger Input INT9 0 1 Push pull output 1 0 Open drain Output 1 1 Input mode with Pull Up...

Page 49: ...R W R W R W Bit Description 7 6 Port E 3 Configuration Bits 0 0 Schmitt trigger Input 0 1 Push pull output 1 0 Open drain Output 1 1 Input mode with Pull Up 5 4 Port E 2 Configuration Bits 0 0 Schmitt trigger Input 0 1 Push pull output 1 0 Open drain Output 1 1 Input mode with Pull Up 3 2 Port E 1 Configuration Bits 0 0 Schmitt trigger Input 0 1 Push pull output 1 0 Open drain Output 1 1 Input mod...

Page 50: ... E 6 Configuration Bits 0 0 Schmitt trigger Input 0 1 Push pull output 1 0 Open drain Output 1 1 Input mode with Pull Up 3 2 Port E 5 Configuration Bits 0 0 Schmitt trigger Input 0 1 Push pull output 1 0 Open drain Output 1 1 Input mode with Pull Up 1 0 Port E 4 Configuration Bits 0 0 Schmitt trigger Input 0 1 Push pull output 1 0 Open drain Output 1 1 Input mode with Pull Up PED Port E Data Regis...

Page 51: ...er Input 0 1 Push pull output 1 0 Open drain Output 1 1 Input mode with Pull Up 5 4 Port F 2 Configuration Bits 0 0 Schmitt trigger Input 0 1 Push pull output 1 0 Open drain Output 1 1 Input mode with Pull Up 3 2 Port F 1 Configuration Bits 0 0 Schmitt trigger Input 0 1 Push pull output 1 0 Open drain Output 1 1 Input mode with Pull Up 1 0 Port F 0 Configuration Bits 0 0 Schmitt trigger Input 0 1 ...

Page 52: ... F 6 Configuration Bits 0 0 Schmitt trigger Input 0 1 Push pull output 1 0 Open drain Output 1 1 Input mode with Pull Up 3 2 Port F 5 Configuration Bits 0 0 Schmitt trigger Input 0 1 Push pull output 1 0 Open drain Output 1 1 Input mode with Pull Up 1 0 Port F 4 Configuration Bits 0 0 Schmitt trigger Input 0 1 Push pull output 1 0 Open drain Output 1 1 Input mode with Pull Up PFD Port F Data Regis...

Page 53: ...4 Port G 2 Configuration Bits 0 0 Schmitt trigger Input 0 1 Push pull output 1 0 Open drain Output 1 1 Input mode with Pull Up 3 2 Port G 1 Configuration Bits 0 0 Schmitt trigger Input 0 1 Push pull output 1 0 Open drain Output 1 1 Input mode with Pull Up 1 0 Port G 0 Configuration Bits 0 0 Schmitt trigger Input 0 1 Push pull output 1 0 Open drain Output 1 1 Input mode with Pull Up PGD Port G Data...

Page 54: ...errupt Enable 1 X Rising Falling Edge Interrupt Enable 5 4 Port A 2 EXTINT2 Interrupt Signal Selection Bit 0 0 Falling Edge Interrupt Enable 0 1 Rising Edge Interrupt Enable 1 X Rising Falling Edge Interrupt Enable 3 2 Port A 1 EXTINT1 Interrupt Signal Selection Bit 0 0 Falling Edge Interrupt Enable 0 1 Rising Edge Interrupt Enable 1 X Rising Falling Edge Interrupt Enable 1 0 Port A 0 EXTINT0 Inte...

Page 55: ...rrupt Signal Selection Bit 0 0 Falling Edge Interrupt Enable 0 1 Rising Edge Interrupt Enable 1 X Rising Falling Edge Interrupt Enable 1 0 Port B 4 EXTINT4 Interrupt Signal Selection Bit 0 0 Falling Edge Interrupt Enable 0 1 Rising Edge Interrupt Enable 1 X Rising Falling Edge Interrupt Enable PINTD2 External Interrupt Direction Control Register Bank1 11H Bit 7 6 5 4 3 2 1 0 See Also Reset Value 0...

Page 56: ...A Reload Interval Selection Bit 0 Reload from 8 bit up counter overflow 1 Reload from 6 bit up counter overflow 1 PWM0 Counter Clear Bit Auto Cleared 0 No effect 1 Clear the PWM counter when write 0 PWM0 Enable Bit 0 Stop counter 1 Start Resume countering PWM0DAT PWM0 Data Register Bank2 0DH Bit 7 6 5 4 3 2 1 0 Related Register Reset Value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit De...

Page 57: ... 0 See Also Reset Value 0 0 0 0 0 0 R W R W R W R W R W R W R W Bit Description 7 SIO Shift Clock Selection Bit 0 Internal clock P S clock 1 External clock SCLK 6 Data Direction Control Bit 0 MSB first mode 1 LSB first mode 5 SIO Mode Selection Bit 0 Receive only mode 1 Transmit receive mode 4 Shift Clock Edge Selection Bit 0 Tx at falling edge Rx at rising edge 1 Tx at rising edge Rx at falling e...

Page 58: ...R W Bit Description 7 0 SIO Prescaler Value STAT System Flags Register 03H Bit 7 6 5 4 3 2 1 0 See Also Reset Value 0 0 0 0 0 0 0 Instruction Summary R W R W R W R W R W R W R W R W Bit Description 7 Global Interrupt Enable Bit 0 Disable All Interrupts 1 Enable All Interrupts 6 ROM Page Selection Bit 0 Page 0 1 Page 1 5 4 SRAM Bank Selection Bit 0 0 Bank 0 0 1 Bank 1 1 0 Bank 2 1 1 Not Used 3 Not ...

Page 59: ...ister Bank0 0EH Bit 7 6 5 4 3 2 1 0 See Also Reset Value 0 0 0 0 0 0 R W R W R W R W R W R W R W Bit Description 7 Timer 0 Mode Selection Bits 0 8 Bit Timer Mode 1 16 Bit Timer Mode 6 4 Timer 0 Clock Selection Bit 0 0 0 fSYS 512 0 0 1 fSYS 256 0 1 0 fSYS 64 0 1 1 fSYS 8 1 0 0 fSYS 1 1 0 1 fSUB SUB Clock 1 1 X T0CLK 3 Timer 0 Counter Clear Bit Auto Cleared 0 No effect 1 Clear the timer 0 counter wh...

Page 60: ... R W R W R W Bit Description 7 Not Used 6 4 Timer 1 Input Clock Selection Bit 0 0 0 fSYS 512 0 0 1 fSYS 256 0 1 0 fSYS 64 0 1 1 fSYS 8 1 0 X fSYS 1 1 1 X fSUB SUB Clock 3 Timer 1 Counter Clear Bit Auto Cleared 0 No effect 1 Clear the timer 0 counter when write T1Data load to T1Buf 2 Timer 1 Start Stop Control Bit 0 Stop Timer 0 1 Start Resume Timer 0 1 0 Not Used T0DATA TIMER 0 Data Register Bank0...

Page 61: ... fSYS 128 1 fSUB Sub Clock 6 4 Not Used 3 2 Timer 2 Interval Selection Bit Must be set T2CON 7 to 1 0 0 1 0 sec Interval 0 1 0 5 sec Interval 1 0 0 25 sec Interval 1 1 1 256 sec Interval 1 Not Used 0 Timer 2 Enable Bit 0 Stop Timer 1 Start Timer WDTE WatchDog Timer Control Register 09H Bit 7 6 5 4 3 2 1 0 Related Register Reset Value R W Bit Description 7 0 WatchDog Timer Control Register This reg...

Page 62: ...Interrupt generation Match Output Port T0OUT only Timer 0 External Clock Input T0CLK only Timer 0 TIMER0 1 control register T0CON T1CON Two operating mode Two 8 bit timer One 16 bit timer combined two 8 bit timer T0CNT T1CNT T0 Comparator T1 Comparator T0 BUF T1 BUF M U X M U X T0CON 7 Timer 1 Overflow T0DATA T1DATA T0OUT T0PND INTCON1 4 T0 Match T1 Match T0CON 7 T1 Match T1PND 64 8 1 fSUB 256 512...

Page 63: ...and mode selection One 16 Bit Mode Function Description In 16 bit mode timer 0 counts upper 8 bit and timer 1 counts lower 8 bit Input clock is selected by timer 0 control register T0CON and timer 1 overflow signal is provided as timer 0 input clock Timer 1 control register T1CON is meaningless in 16 bit mode Timer 1 interrupt is not generated Only timer 0 interrupt is generated which represents 1...

Page 64: ...TART CALL BANK_0 MOVLW 1FH MOVWF T0DATA Set T0DATA 31 D MOVLW 00010000B 8 bit Timer Mode MOVWF T0CON T0timer fsys Prescaler Ratio period Data 1 T0 interrupt 8 192M HZ 256 32 1K HZ CALL BANK_1 BSF PACONL 0 BSF PACONL 1 Port A 0 Configuration T0OUT BSF INTCON1 4 Timer 0 Match Interrupt Enable Bit CALL BANK_0 BSF T0CON 3 Timer 0 Counter Clear BSF STAT 7 Enable All Interrupts BSF T0CON 2 Start Timer 0...

Page 65: ...ement Using a Main clock or SUB Clock fSYS 128 or fSUB LCD Clock fLCD Generator fT2 27 fT2 26 fT2 25 fT2 24 Timing Tests in High Speed Mode Overflow interrupt generation 1s 0 5s 0 25s 3 91ms Timer 2 control register T2CON Frequency Divider Interval Selector fT2 27 fT2 213 fT2 214 fT2 215 fLCD fT2 27 Hz T2CON 7 MUX fOSC 128 fSUB T2CON 3 2 INTPND1 6 INT INTCON1 6 T2CON 0 fT2 fLCD fT2 26 Hz fLCD fT2 ...

Page 66: ...M0CON 1 8 or 6 bit Counter Overflow 2 Bit Counter 6 Bit Counter PWM0CON 0 MUX PWM0CON 5 4 64 8 2 1 PA 6 Figure 4 1 Block Diagram The PWM output signal toggles to Low level whenever the lower 6 bit of counter matches the reference data register PWM0DAT 7 2 If the value in the PWM0DAT 7 2 register is not zero an overflow of the lower 6 bits of counter causes the PWM output to toggle to High level In...

Page 67: ...ock PWM0DAT 00000100b PWM0DAT 00000101b PWM0DAT 00000110b PWM0DAT 00000111b Figure 4 2 Extended Output Example 4 1 PWM0 Sample Code fSYS 8 192 MHz 1 Cycle 500μs Extend 2nd Cycle MOVLW MOVWF BSF BSF CLRF BSF BSF 05h PWM0DAT PCCON 6 PCCON 7 PWM0CON PWM0CON 1 PWM0CON 0 Set PWM0 Data Register Data 1 Extension 1 Select PCCON 76 11 PWM0 Out fSYS 64 8 bit Overflow Reload PWM Stop PWM0 Counter Clear PWM0 ...

Page 68: ... enters an idle state 6 The digital conversion result can now be read from the ADDATAH ADDATAL register If the chip enters to STOP mode in conversion process there will be a leakage current path in A D block The ADC operation must be finished before the chip enters STOP mode There is not sampling hold circuit in ADC Therefore it is important that any fluctuations in the analog level at the ADC0 AD...

Page 69: ... 8 7 6 5 4 3 2 1 0 Figure 5 2 A D Conversion Timing Diagram Maximum ADC Input Clock is 4MHz Example 5 1 ADC Sample Code MOVLW MOVWF BSF BSF BSF ADC_LOOP BTFSS GOTO 00000100b ADCCON PBCON 0 PBCON 1 ADCCON 0 ADCCON 3 ADC_LOOP fSYS 4 ADC0 Configure ADCCON Configure PB 0 ADC Input 0 Start Conversion Wait until EOC bit is set Converted value can be read from ADDATL and ADDATH ...

Page 70: ...2 41 Schmitt trigger input Push pull output Open Drain output External Interrupt 2 Clock Output I O 3 42 Schmitt trigger input Push pull output Open Drain output External Interrupt 3 Buzzer Out I O B 4 43 Schmitt trigger input Push pull output Open Drain output ADC4 I O PORTA 5 44 Schmitt trigger input Push pull output Open Drain output ADC5 I O 0 1 Schmitt trigger input Push pull output Open Drai...

Page 71: ... Schmitt trigger Input Push pull output Open Drain output SEG11 I O D 2 0 27 Schmitt trigger Input Push pull output Open Drain output SEG12 I O 1 28 Schmitt trigger Input Push pull output Open Drain output SEG13 I O 2 29 Schmitt trigger Input Push pull output Open Drain output SEG14 I O 3 30 Schmitt trigger Input Push pull output Open Drain output SEG15 I O 4 31 Schmitt trigger Input Push pull out...

Page 72: ... 1 2 2007 03 06 Pin Circuit Pull Up Resister VDD Noise Filter nRESET Figure 6 1 Pin Circuit Type R I O Digital Input P CH Open drain Enable Pull up Enable Output Disable Data N CH VDD VDD External Interrupt Input Figure 6 2 Pin Circuit Type B ...

Page 73: ...7 03 06 I O Digital Input P CH Open drain Enable Pull up Enable Output Disable Data N CH VDD VDD Interrupt Input ADC Input ADC Enable Figure 6 3 Pin Circuit Type C Output Disable COM SEG Out VLC1 VLC2 VLC3 VLC4 VLC5 VLC6 Figure 6 4 Pin Circuit Type D ...

Page 74: ... COM SEG LCD Output Enable Pull Up Resister VDD VDD Pull Up Enable I O External Interrupt Input Digital Input Figure 6 5 Pin Circuit Type D 1 Output Disable Data Circuit D Open Drain Enable COM SEG LCD Output Enable Pull Up Resister VDD VDD Pull Up Enable I O Digital Input Figure 6 6 Pin Circuit Type D 2 ...

Page 75: ... function LCD SEG output SCLK SI SO PWM out LCD Function can be selected in LPCON register PORTD Port D as 2 bit I O Pins It can be used for normal I O Schmitt trigger input push pull output open drain output or some alternative function LCD SEG output External interrupt LCD Function can be selected in LPCON register PORTE Port E has 8 bit I O Pins It can be used for normal I O Schmitt trigger Inp...

Page 76: ...t Control COM3 COM Control COM2 COM1 COM0 COM6 SEG 17 COM5 SEG 18 COM4 SEG 19 LPCON LCDCON 3 2 LCD Buffer LPCON MUX 16 LCDCON 1 0 4 160 fLCD 2048Hz fLCD 1024Hz fLCD 512Hz fLCD 256Hz Timimg Controller Figure 7 1 LCD Controller Block Diagram LCDCON is used to define the timing requirements of the LCD panel input clock duty and bias selection and display on off control Table 7 1 shows COM and SEG pin...

Page 77: ...tch the LCD panel being used The individual bits of the LCD data registers are cleared set to represent a clear dark pixel respectively And the data can be transferred to the segment signal pins automatically without program control Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 SEG0 20h COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG1 21h SEG2 22h 31h SEG17 32h SEG18 33h SEG19 Figure 7 2 LCD Buffer Organiza...

Page 78: ... 3 4 5 6 7 COM0 COM1 COM2 SEG0 SEG0 COM0 VDD VLCD1 VLCD2 VLCD4 VSS VDD VLCD1 VLCD2 VLCD4 VSS VDD VLCD1 VLCD2 VLCD4 VSS VDD VLCD1 VLCD2 VLCD4 VSS VDD 1 4VDD 0V 1 4VDD VSS COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG0 20h SEG1 21h SEG2 22h SEG3 23h SEG4 24h Figure 7 3 LCD Signal 1 8 Duty 1 4 Bias ...

Page 79: ...VLCD1 VLCD2 VLCD3 VLCD4 VSS SEG0 SEG1 0 1 2 3 VDD VLCD1 VLCD2 VLCD3 VLCD4 VSS VDD VLCD1 VLCD2 VLCD3 VLCD4 VSS VDD VLCD1 VLCD2 VLCD3 VLCD4 VSS VDD VLCD1 VLCD2 VLCD3 VLCD4 VSS VDD VLCD1 VLCD2 VLCD3 VLCD4 VSS COM3 SEG1 3 COM0 SEG0 0 COM0 SEG1 0 COM2 SEG0 2 COM1 SEG1 1 COM1 SEG0 1 COM3 SEG0 3 COM2 SEG1 2 Figure 7 4 LCD Signal 1 4 Duty 1 3 Bias ...

Page 80: ... VLCD2 VLCD3 VLCD4 VSS SEG0 SEG1 0 1 2 SEG2 COM2 SEG0 2 COM0 SEG2 0 COM0 SEG1 0 COM1 SEG2 1 COM0 SEG0 0 COM1 SEG0 1 COM1 SEG1 1 COM2 SEG1 2 VDD VLCD1 VLCD2 VLCD3 VLCD4 VSS VDD VLCD1 VLCD2 VLCD3 VLCD4 VSS VDD VLCD1 VLCD2 VLCD3 VLCD4 VSS VDD VLCD1 VLCD2 VLCD3 VLCD4 VSS VDD VLCD1 VLCD2 VLCD3 VLCD4 VSS Figure 7 5 LCD Signal 1 3 Duty 1 3 Bias ...

Page 81: ...bit PC 1 as Buzzer out function When the Buzzer Out is enabled the 6 bit counter is cleared and PC 1 output status is 0 and start counting up If the counter value is match up to period data BZCON 5 0 then PC 1 output status is toggle and the counter is cleared Also the counter is cleared by 6 bit counter overflow BZCON 5 0 determines output frequency Frequency calculation is as follows FBZ fSYS 2 ...

Page 82: ... BZCON PACONL 6 PACONL 7 PACONL 7 PACONL 6 fSYS 64 Period Data 9 6 4 KHz Output Set Buzzer 1KHz Output Set PA 3 Buzzer out Set PA 3 Input mode Buzzer Disable Buzzer Counter Buffer Reload Buzzer Output Buzzer Data Change Before After Buzzer Data Change Before After Buzzer Disable Buzzer Enable Figure 8 2 Timing Diagram ...

Page 83: ...gister SIOCON Clock selector logic 8 bit data buffer SIODAT 8 bit prescaler SIOPS 3 bit serial clock counter Serial data I O pins SI SO Serial clock input output pin SCLK The SIO module can transmit or receive 8 bit serial data at a frequency determined by its corresponding control register settings To ensure flexible data transmission rates you can select an internal or external clock source Figu...

Page 84: ...d SIO CONTROL REGISTERS SIOCON The control register for serial I O interface module SIOCON It has the control setting for SIO module Clock source selection internal or external for shift clock Edge selection for shift operation Clear 3 bit counter and start shift operation Shift operation transmit enable Mode selection transmit receive or receive only Data direction selection MSB first or LSB firs...

Page 85: ... D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SO SCLK IRQ SET SIOCON 3 Transmit Complete Figure 9 2 SIO Transmit Receive Mode Tx at falling edge SI D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SO SCLK IRQ SET SIOCON 3 Transmit Complete Figure 9 3 SIO Transmit Receive Mode Tx at rising edge ...

Page 86: ...UM TM59PA80_E 85 tenx technology inc Rev 1 2 2007 03 06 SI D7 D6 D5 D4 D3 D2 D1 D0 High Impedance SO SCLK IRQ SET SIOCON 3 Transmit Complete Figure 9 4 SIO Receive Only Mode Rising edge start ...

Page 87: ...IH1 Except XIN XOUT 0 8 VDD Input High Voltage VIH2 XIN XOUT VDD 2 0 to 5 5 V VDD 0 5 VDD VIL1 Except XIN XOUT 0 2 VDD Input Low Voltage VIL2 XIN and XOUT VDD 2 0 to 5 5 V 0 5 VOH1 PB 0 1 PD 4 6 VDD 2 4V IOH 4mA VDD 0 7 VDD 0 3 VOH2 PC VDD 5V IOH 4mA VDD 1 0 Output High Voltage VOH3 Normal output pins VDD 5V IOH 1mA VDD 1 0 VOL1 PB 0 1 PD 4 6 VDD 2 4V IOH 12mA 0 3 0 5 VOL2 PC VDD 5V IOH 15mA 0 4 2...

Page 88: ... 0 8VDD 0 8VDD 0 2 VLCD2 0 6VDD 0 2 0 6VDD 0 6VDD 0 2 VLCD3 0 4VDD 0 2 0 4VDD 0 4VDD 0 2 LCD Voltage VLCD4 VDD 2 7V to 5 5V 1 5 bias LCD clock 0Hz VLCD0 VDD 0 2VDD 0 2 0 2VDD 0 2VDD 0 2 V VDD 5 V 10 8 MHz 12 25 VDD 5 V 10 4 MHz 4 10 VDD 3 V 10 8 MHz 3 8 IDD1 VDD 3 V 10 4 MHz 1 5 Idle VDD 5 V 10 8 MHz 3 10 Idle VDD 5 V 10 4 MHz 1 5 4 Idle VDD 3 V 10 8 MHz 1 2 3 IDD2 Idle VDD 3 V 10 4 MHz 1 0 2 0 mA...

Page 89: ...nit VDD 2 5 to 5 5 V 0 4 12 External Clock fOSC VDD 2 0 to 5 5 V 0 4 4 2 VDD 5 0 V 0 4 2 External RC NOTE 1 fOSC VDD 3 0 V 0 4 1 MHz SUB Clock fSUB 32 32 768 35 KHz NOTE 1 Tolerance 10 at TA 25 C XIN XOUT XIN XOUT External Oscillator Circuit Crystal or Ceramic External R C Oscillator XTIN XTOUT Sub Clock Oscillator Circuit Crystal or Ceramic ...

Page 90: ...me tSCLK Internal SCLK Source 1 000 External SCLK Source 500 SCLK high low width tSH tSL Internal SCLK Source TSCLK 2 50 External SCLK Source 250 SI setup time SCLK high tSIS Internal SCLK Source 250 External SCLK Source 400 SI hold time SCLK high tSIH Internal SCLK Source 400 External SCLK Source 300 Output delay SCLK to SO tSOD Internal SCLK Source 250 ns tSL tSH tSCLK tSIH tSIS tSOD SCK SDI SDO...

Page 91: ... Interrupt Input Width tINTH tINTL VDD 5 V 10 200 ns 0 8VDD tINTH tINTL 0 2VDD 10 6 Reset Timing Characteristics TA 40 C to 85 C VDD 2 0V to 5 5V Parameter Conditions Min Typ Max Unit Input High Voltage 0 8 VDD VDD V Input Low Voltage 0 2 VDD V Reset Input Low Width Input VDD 5 V 10 2 μs 10 7 LVD Circuit Characteristics TA 40 C VDD 2 0V to 5 5V Parameter Symbol Min Typ Max Unit LVD reference Volta...

Page 92: ... 3 Offset Error of Bottom VDD 5 12 V VSS 0 V CPU clock 10 MHz 1 2 LSB Max Input Clock fADC 4 MHz Conversion Time NOTE 1 fADC 4 MHz 20 μs Analog Input Voltage VSS VDD V Analog Input Impedance 2 MΩ Analog Input Current VDD 5 V 10 μA VDD 5 V 1 3 mA VDD 3 V 0 5 1 5 mA Analog Block Current Note 2 VDD 5 V stop mode 100 500 nA NOTE 1 Conversion time is the time required from the moment a conversion opera...

Page 93: ...X YY C Z y IC TYPE TM59PA80 y XX Package Type 1 QFP Code QF 2 DIP SKINNY Code SD 3 LQFP Code LQ 4 DIP Code DP y YY IC Pin Number 1 Pin Number 44 Code 44 2 Pin Number 42 Code 42 3 Pin Number 40 Code 40 y C Reserve Must write be C y Z Package material 1 Package material Pb free Code W 2 Package material Green Package Code G ...

Page 94: ...enx technology inc Rev 1 2 2007 03 06 11 1 44 QFP Package Dimension 44 lead Quad Flat Package Dimension in Millimeters 44 QFP 2 05 0 10 MAX 2 30 MIN 0 05 0 80 0 20 10 00 0 20 13 20 0 30 0 35 0 10 0 80 1 00 0 15 0 10 0 8 ...

Page 95: ... 1 2 2007 03 06 11 2 42 SDIP Package Dimension 42 lead Shrink Dual In line Package Dimension in Millimeters 1 22 42 SDIP 14 40 0 20 MAX 39 50 39 10 0 20 1 77 0 50 0 10 1 00 0 10 1 778 MIN 0 51 3 30 0 30 3 50 0 20 MAX 5 08 0 15 0 25 0 10 15 24 ...

Page 96: ...UM TM59PA80_E 95 tenx technology inc Rev 1 2 2007 03 06 11 3 44 LQFP Package Dimension 44 lead Shrink Dual In line Package Dimension in Millimeters ...

Page 97: ...UM TM59PA80_E 96 tenx technology inc Rev 1 2 2007 03 06 11 4 40 DIP Package Dimension 40 lead Shrink Dual In line Package Dimension in Millimeters ...

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