NL865H2 Hardware Design Guide
1VV0301616 Rev. 7
Page
30
of
67
2020-04-20
The RST timing is shown in the following figure below:
5.3.2.
Operating levels
The
RESET*
line is connected to VBATT with a Pull Up so the electrical levels on this pin
are aligned to the main supply level.
WARNING:
The hardware unconditional Reset must not be used during normal
operation of the device since it does not detach the device from the network.
It shall be kept as an emergency exit procedure.
The RST circuit design is divided into two types:1.8V and non-1.8V.
The 1.8V RST
reference circuit design is shown below. The resistor value is for reference only. Please
fine tune according to the specific application:
