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Teledyne
LeCroy
DDR3
and
DDR4
JEDEC
Timing
Violations
Summary
158
Kibra
DDR
Protocol
Analyzer
User
Manual
5.1.10
V10 - t RFC REFRESH to a Valid Command
Defines
the
minimum
interval
between
Refresh
and
the
next
valid
command
to
the
same
bank.
The
table
outlines
the
minimum
interval
while
the
maximum
(between
two
refresh
commands)
is
defined
by
9
×
Refresh
Interval
(tREFI).
5.1.11
V11 - tREFI REFRESH Interval
A
Refresh
command
needs
to
be
issued
every
tREFI
interval
and
a
maximum
of
8
Refresh
commands
can
be
postponed
during
SDRAM
operation.
Thus,
in
the
event
8
Refresh
commands
are
postponed
in
a
row,
the
maximum
interval
between
two
Refresh
commands
would
never
exceed
9
×
tREFI.
After
exiting
Self
‐
Refresh
Mode
with
one
or
more
Refresh
commands
postponed,
additional
Refresh
commands
may
be
postponed
to
the
extent
that
the
total
number
of
postponed
Refresh
commands
(before
and
after
the
Self
‐
Refresh)
will
never
exceed
eight.
During
Self
‐
Refresh
Mode,
the
number
of
postponed
or
pulled
‐
in
REF
commands
does
not
change.
5.1.12
V12 - tRTR READ to READ delay (DDR3 - same rank) (DDR4 - same bank
group)
Defined
as
the
interval
between
a
single
READ
command
and
another
l
READ
to
the
same
rank
and
the
same
DIMM.
This
is
calculated
based
on
the
CAS
to
CAS
delay
(tCCD)
which
is
a
minimum
of
4
CKs
for
all
speed
bins.
5.1.13
V13 - tdrRTR READ to READ delay (different rank - same DIMM)
Defined
as
the
interval
between
a
single
READ
command
and
another
READ
to
a
different
rank
within
the
same
DIMM.
Read
bursts
to
a
different
rank
are
based
on
the
CAS
to
CAS
delay
(tCCD).
Timing
between
commands
to
a
different
rank
or
DIMM
should
be
vendor
specified.
5.1.14
V14 - tddRTR READ to READ delay (different DIMM)
Defined
as
the
interval
between
a
READ
command
and
another
READ
to
a
different
DIMM.
Timing
between
commands
to
a
different
rank
or
DIMM
should
be
vendor
specified.
Speed
Grade
800
1066
1333
1600
1866
Min
(ns)
90
110
160
300
350
Speed
Grade
Case
Temp
800
1066
1333
1600
1866
Min
(
μ
s)
0
°C
≤
TCASE
≤
85
°
7.8
7.8
7.8
7.8
7.8
Min
(
μ
s)
85
°C
<
TCASE
≤
95
°C
3.9
3.9
3.9
3.9
3.9
Summary of Contents for Kibra DDR
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