TMS 540 PowerPC 60X Microprocessor Support Instruction Manual
Index–1
Index
Numbers
32-Bit bus configuration, 2–14
64-Bit bus configuration, 2–14
A
about this manual set, xi
acquiring data, 2–7
Address group
channel assignments, 3–4
display column, 2–12
address pipelining, 1–3
Alt Byte Ord - Hi Bound field, 2–14
Alt Byte Ord - Lo Bound field, 2–14
alternate connections
extra channel probes, 3–15
to other signals, 3–15
B
basic operations, where to find information, xi
Big-Endian byte order, 2–14
Bus Config/Proc Select field, 2–13
bus cycles
Address cycle types, 2–8
ARTRY, DRTRY, and Data Error, 2–10
Data cycle types, 2–9
Direct Store Access cycle types, 2–9
displayed general cycle types, 2–10
bus timing, 3–14
C
certifications, 3–1
channel assignments
192-channel module
Com_60X group, 3–10
PPC601_4 group, 3–10
PPC603_4 group, 3–11
PPC604 group, 3–12
Address group, 3–4
clocks, 3–12
Control group, 3–8
Hi_Data group, 3–6
Lo_Data group, 3–7
Misc group, 3–9
Transfer group, 3–8
Tsiz group, 3–9
channel groups, 2–1
clock channel assignments, 3–12
clock rate, 1–3
clocking, Custom, 2–1
how data is acquired, 3–13
clocking options
DRTRY Cycles, 2–2
field names, 2–2
how data is acquired, 3–14
Com_60X group, 192-channel module, channel
assignments, 3–10
compliances, 3–1
connections
no probe adapter, 1–11
136-channel module, 1–12
192-channel module, 1–14
other microprocessor signals, 3–15
probe adapter to SUT
MPC601 and PPC601 converter clip, 1–4
MPC603 and PPC603 converter clip, 1–4
Control Flow display format, 2–12
Control group
channel assignments, 3–8
symbol table, 2–3
Custom clocking, 2–1
DRTRY Cycles, 2–2
how data is acquired, 3–13
cycle types
Address, 2–8
ARTRY, 2–10
combined labels, 2–8
Data, 2–9
Data Error, 2–10
Direst Store Access, 2–9
DRTRY, 2–10
general, 2–10
D
data
acquiring, 2–7
disassembly formats
Control Flow, 2–12
Hardware, 2–8
Software, 2–12
Subroutine, 2–12
how it is acquired, 3–13
data display, changing, 2–13
