Specifications
Digital IQ Output Timing
All I/Q signals output from the FPGA are synchronous to the 200 MHz
Acquisition Data clock, received over the high-speed LVDS interface from the
digital interface board; all signals are registered at the FPGA pins. (See Table 69.)
The IQ clock is generated so as to have a 50% duty cycle (±5%), regardless of
clock rate. The IQ clock is set so that it has the rising edge in the center of the
settled data and DAV signals, which allows near symmetric setup and hold time.
Table 68: EXT_IQ_DAV Duty cycle versus Span
Span
EXT_IQ_CLK frequency (MHz)
EXT_IQ_DAV duty cycle (%)
60 MHz
200
50.0
40 MHz
50
100.0
20 MHz
50
50.0
10 MHz
50
25.0
5 MHz
50
12.5
2 MHz
50
6.250
1 MHz
50
3.125
500 kHz
50
1.5625
200 kHz
50
0.78125
100 kHz
50
0.39063
50 kHz
50
0.19531
20 kHz
50
0.097656
10 kHz
50
0.048828
5 kHz
50
0.024414
2 kHz
50
0.006104
1 kHz
50
0.003052
500 kHz
50
0.001526
200 kHz
50
0.000763
100 kHz
50
0.000381
The rising edge of EXT_IQ_CLK is aligned to be in the center of the settled
EXT_I[15:0], EXT_Q[15:0], and EXT_IQ_DAV signals.
68
RSA5100B Series Technical Reference
