Locating Signals
The SPI bus signals are set as follows:
SCLK is the rising edge latch
SS is active low
MOSI is active high
This is the beginning of the mixed signal chain. See the descriptions of these signals: DAC Input, Parallel, and DAC Output.
Packets occur approximately every 5 ms. The SPI packet contents are transferred to the Parallel DAC Input bus at the end of the
packet. The Parallel DAC Input bus then changes the voltage output of the DAC.
The resulting DAC output is a sine wave with an amplitude of 0 to 3 volts, and a period of 310 ms.
The clock rate is a 100 kHz, 0 to 5 volt signal.
Figure 2: Mixed signal chain block diagram
Demo 2 Board Instruction Manual
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Summary of Contents for DPO2000 Series
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