Tektronix 7623, Instruction Manual

Page: 64 / 266

Circuit Description—7623/R7623 Service
Readout system is ready to display Readout information,
the level at pin 6 goes HI. This level blocks the signals from
both vertical compartments and there is no output from
U214 under this condition. Transistor Q238 will conduct
and provide about the same current for the output stage as
under normal conditions. This limits any change in posi­
tioning that would otherwise occur when the X/Y Shut­
down signal from the Readout system is applied.
Fig. 3-17. Input/output table for Vertical Channel Switch.
Auxiliary Y-Axis Input Amplifier
The Auxiliary Y-Axis Input Amplifier accepts an input
from horizontal plug in units having compatible features.
Normally, this input is a positioning voltage to offset the
display. The single-ended signal connected to the input of
this stage is converted to a push-pull signal at the collectors
of 0225 and Q236. This signal is connected to the
Delay-Line Buffer stage along with the output from the
Vertical Channel Switch.
pins 12 and 13 is always equal to the sum of the DC input
currents at pins 1, 8, 9, and 16 in all modes. This provides a
constant DC bias to the following stage as the VERT
MODE switch is changed.
When the VERT MODE swich is set to LEFT, the level
at pin 4 is LO. This level allows the signal from the left
vertical unit to pass to the output while the signal from the
right vertical unit is blocked. In the RIGHT position of the
VERT MODE switch, the level at pin 4 is HI. Now, the
signal from the right vertical unit is connected to the
output while the signal from the left vertical unit is
blocked.
When the VERT MODE switch is set to either ALT or
CHOP, the Mainframe Vertical Mode Command at pin 4
switches between the LO and HI levels at a rate determined
by either the Chop Counter or the Vertical Binary stages
(see Logic circuit description). This action allows the signal
from the left vertical unit to be displayed when the
Mainframe Vertical Mode Command is LO and the signal
from the right vertical unit is displayed when the Main­
frame Vertical Mode Command is HI. When ADD vertical
mode operation is selected, a HI level is applied to pin 14
and the level at pin 4 is LO as determined by the Vertical
Mode Control stage in the Logic Circuit. This allows both
the right and left vertical signals to pass to the output pins.
Now, the signal from both vertical units is algebraically
added and the resultant signal determines the vertical
deflection.
The X/Y Shutdown signal from the Readout system is
applied to pin 6 of U214. It has final control over the
output signal from U214. Quiescently, the X/Y Shutdown
signal is LO and the signal from the selected vertical can
pass to the output pins 12 and 13. However, when the
Delay-Line Buffer
The output of the Vertical Channel Switch stage, along
with any signal from the Auxiliary Y-Axis Input Amplifier,
is connected to the emitters of Q242-Q252. These tran­
sistors are connected as common-base amplifiers to provide
a low-impedance current-summing point. The signal at the
collectors of Q242-Q252 is connected to Delay Line
DL400. Resistor R260 provides reverse termination for the
Delay Line.
Delay Line
Delay Line DL400 provides approximately 150 nano­
seconds delay for the vertical signal, to allow the horizontal
circuits time to initiate a sweep before the vertical signal
reaches the vertical deflection plates of the CRT. This
allows the instrument to display the leading edge of the
signal originating the trigger pulse when using internal
triggering. The delay line used in this instrument has a
characteristic impedance of about 50 ohms per side, or
about 100 ohms differentially. It is of the coaxial type,
which does not produce preshoot or phase distortion in the
CRT display.
VERTICAL AMPLIFIER
The Vertical Amplifier circuit provides final amplifica­
tion for the vertical signal before it is applied to the vertical
deflection plates of the CRT. This circuit includes an input
from the BEAM FINDER switch to compress an over­
scanned display within the viewing area of the CRT. Fig.
3-18 shows a detailed block diagram of the Vertical
Amplifier circuit. A schematic of this circuit is shown on
diagram 4 at the rear of this manual.
3-20