Tektronix 7623, Instruction Manual

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Circuit Description— 7623/R7623 Service
limiting, the Intensity Limit input goes to ground level in
the plug-in unit. This reduces the level of 11 at the base of
U99D and therefore reduces I, and the output current to
reduce the intensity of the display. At the same time, the
ground level from the Intensity Limit input is connected to
the emitter of Q90B through R80. This connection limits
the maximum level to which the INTENSITY control can
be set to aid in obtaining intensity limiting at slow sweep
rates.
The collector current of U99D is made up of two
currents; ls and l2 is determined by divider R92 and R93.
When the Sweep Gate level at the base of U99A is LO (no
sweep in progress), l2 is at its maximum level so that ls is
minimum to provide minimum intensity of the display (ls +
l 2 is always equal to lt). During sweep time, the Sweep
Gate level at the base of U99A as established by
INTENSITY control R102 determines the output current.
As the INTENSITY control is turned toward maximum, the
level of l2 decreases. This allows ls to increase to produce a
brighter display. The Auxiliary Z-Axis Inputs from the
plug-in compartments and the intensity modulating signal
from the EXT Z-AXIS input connector are connected to
the emitter of Q90B. These signals modulate the level of l2
to, in turn, modulate the intensity of the display.
When readout information is to be displayed on the
CRT, the Z-Axis shutdown goes LO. This forward biases
Q180, and it saturates, shunting l1( through Q108 to
ground. 1 his reduces the output current to zero during the
readout time.
Clock Generator
One half of integrated circuit U55 along with the
external components shown in Fig. 3-4A make up the
Clock Generator stage. R1, Q1. Q2, and Q3 represent an
equivalent circuit contained within U55A. This circuit
along with discrete components C59, R56, R57, and R59
comprise a two-megahertz free-running oscillator to provide
a timing signal (clock) for mainframe vertical and plug-in
chopping.
The stage operates as follows: Assume that Q2 is
conducting and Q1 is off. The collector current of Q2
produces a voltage drop across R1 which holds Q1 off. This
negative level at the collector of Q2 is also connected to pin
14 through Q3 (see waveforms in Fig. 3-4B at time To).
Since there is no current through Q1, C59 begins to charge
towards —15 volts through R56 R57. The emitter of Q1
goes negative as C59 charges until it reaches a level about
0.6 volt more negative than the level at its base. Then, QI is
forward biased and its emitter rapidly rises positive. Since
3-9