Tektronix 318, Technical Manual

Page: 81 / 555

TM 11-6625-3145-14
Theory of Operation-318/338 Service
Full Valid Flag Latch. The full valid flag latch consists of A04U139B. It provides the full valid data display mode. This
latch is set by the SET F VALID signal and reset by the RESET signal from the A03 ACQ board.
LSI-B (A04U140). A04U140 is a Sony/Tektronix-designed hybrid chip that provides simplified circuit construction and
reduced circuit board space and power consumption. Its circuity consists of an address decoder, divider, timer, and slow-
clock detector.
The address decoder circuit consists of four decoders that enable the MPU to select the sample interval, gate clock
interval, timer clock interval, or step clock . The address decoder provides the necessary pulses for the initialization and
presetting of these circuits. The selection is made by two bits of address and six bits of data from the MPU when CS1X is
low.
The divider circuit consists of a 7-stage decade counter, and divide-by-2 and divide-by-5 counters based on a ring counter
circuit. The output of these counters is delivered as the INTCLK signal via the 1-2-5 sequence selector.
The timer circuit consists of an output latch which is reset by the RDSTS signal from the A03 ACQ Control board. It
generates a constant interval timing signal ranging from one to five multiples of the internally generated 100 ms clock.
The slow clock detector circuit consists of two shift registers and a control flip-flop. The CLKSLW signal is initialized to
high level by the RDSTS signal.
If the SYSCLK signal is either high or low for two or more consecutive pulses, the internal shift registers are not clocked,
and the low level at the input of the first shift register bit is not transferred to the second shift register; this causes the
CLKSLW signal to be output.
When the SYSCLK is less than 25 ms (slow rate) the shift registers are clocked by SYSCLK. But the CLKSLW output is
not changed because a control gate of the shift register closes before the second rising edge of SYSCLK arrives.
When the SYSCLK rate is fast (above 25 ms), the low-level pulse provided is successfully transfered to the CLKSLW
output via the first and second shift registers.
The CLKSLW output’s four conditions (high, slow, low, and fast) must be read before the start of each gate timing,
because the CLKSLW signal is changed by the gated SYSCLK.
The function of each signal for the U140 is as follows:
4-20