Tektronix 318, Technical Manual

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TM 11-6625-3145-14
Theory of uperation-318/338 Service
TIMEBASE AND MPU BUS INTERFACE <9>
The timebase and MPU bus interface circuit consists of the frequency divider, timer, slow clock detector, INTCLK buffer,
data selector, full valid flag latch, TTL-to-ECL translater, ECL-to-TTL translator, and address decoder. A simplified
diagram of this circuit is given in Figure 4-7.
TTL-to-ECL Translator. The TTL-to-ECL translator consists of A04U100, A04U102, A04U104, A04U106, and A04U108.
It accepts a TTL-level signal from the MPU bus and translates it into a differential ECL-level signal.
Address Decoder. The address decoder consists of A04U112C and A04U110. It provides the chip-select and enable
signals which select the specific device needed to communicate with the MPU. This selection is made by outputs from the
3-line-to-8-line decoder, A04U110. Gate A04U112C supplies the I/O enable signal, EN (which is an ORed signal of BRD
and BWR).
Oscillator. The oscillator circuit consists of A04U112A and A04U112B. Crystal A04Y100, and A04U112A form a 100
MHz crystal-controlled oscillator. The 100 MHz oscillator is buffered by A04U112B before being divided by A04U140
(LSI-B).
Divider, Timer, and Slow Clock Detector. The divider, timer, and slow clock detector are contained on LSI-B
(A04U140). More information about LSI-B is provided under the LSI-B (A04U140) paragraph later in this section.
The frequency divider provides the 20 ns to 500 ms clock output. A clock output is determined by the internal timebase
selection register. The selected internal clock signal is sent to the INTCLK buffer A04U112D. The INTCLK selection data
is shown in Table 4-5.
The timer generates the selected constant interval signal for an interrupt to the MPU. This signal is reset by the RDSTS
signal.
The slow-clock detector circuit provides the capability to detect a slow sampling clock rate (clock less than 25 ms) in the
external clock operation mode. When the clock rate is slow, the CLKSLW signal holds a high state and the MPU displays
SLOW CLOCK on the screen. The timing diagram of the timer and the slow-clock detector circuit is shown in Figure 4-8.
INTCLK Buffer. The INTCLK buffer consists of A04U112D. It provides a power boost and improves the waveform shape
for INTCLK signals on the bus.
Data Selector. The data selector consists of A04U142 and A04U144. It provides data selection of either acquisition
memory output or acquisition status output. This data selector is controlled by the READ ACQ DATA signal.
When the MPU reads the acquisition memory data, it sets the SELECT input (pin 9, READ ACQ DATA signal) to high, and
connects the acquisition memory data to the data selector output. If the SELECT input is low, acquisition status is
selected, and the MPU reads acquisition status as data.
ECL-to-TTL Translator and TTL Bus Buffer. The ECL-to-TTL translator and TTL bus buffer consists of A04U146,
A04U148, A04U150, A04U156, and A04U152. The ECL-to-TTL translator receives ECL-level signals from data selectors
A04U142 and A04U144. A04U146, A04U148, and A04U150 are ECL-to-TTL translators with totem-pole outputs.
A04U156 is a comparator with open-collector output for wired-AND capability. The TTL bus buffer, A04U152, provides
power boost with tri-state control for the I/O common bus. It is enabled by the RD and OE signals.
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