Tektronix 318, Technical Manual

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TM 11-6625-3145-14
Theory of Operation-318/338 Service
M218’s glitch trigger outputs moves to high. A02U224 <21> receives the glitch trigger enable data serially and sends it to
the M218s in parallel. A02U224 controls the M218's pin 15. This is a shift register and can have data written to it in serial.
Data writtern to this shift register from the MPU is adjusted by A02U226 to fit M218's special input level requirements.
WORD RECOGNIZER <21>
The word recognizer (WR) consists of three 32-channel word recognizers incorporating high-speed memories. The 338
offers three WR functions, where three different words may be set up at once. They are named trigger words A, B, and C.
To load data into the WRs, the MPU resets the WR address counters A01U100 <19>, A01U102 <19½>, A01U104 <19>,
A01U106 <19>, A01U108 <19>, A01U110 <19>, A02U220 <21> and A02U222 <21>. The MPU then writes the data
according to the trigger words eight channels at a time. If the WR address counter value is equal to the trigger word, 0 is
written into the corresponding WR; otherwise 1 is loaded. The MPU then increments these WR address counters by one
and loads data as above. This operation is repeated 256 times. For example, if the trigger word A is 78310827
hex
, the
MPU resets the WR address counters and increments A01U104 and A01U106 to 08, and writes 0 to A01 U118 pin 6. The
MPU then increments A01U108 and A01U110 to 27 and writes 0 to A01U120 pin 6. Then it increments A01U100 and
A01U102 to 31 and writes 0 to A01U122 pin 6, and increments A02U220 and A02U222 to 78 and writes 0 to U218 pin 6.
A1 is written into the other addresses. Before an acquisition starts, these WR address counter outputs are reset to 0, and
the MPU changes 10016's on the A01 board to latch mode and sets the output of M218s on the A02 board to on. During
an acquisition, if the trigger word is latched, the corresponding WR issues a 0 and that trigger line goes to 0.
THRESHOLD BUFFER <22>
The currents from the edge-connecter 38B, 39A, 39B, and 40A are applied to the inverting inputs of A02242A, A02U242B,
A02U242C, and A02U242D <22> which have a gain of minus one. The currents from pin 5 of J200, J202, J204, and J206
are supplied to the non-inverting inputs of these amplifiers to be summed. The output currents of these amplifiers are
supplied through A02R234A, A02R234B, A02R234C, and A02R234D, respectively, to the parallel data probe.
PROBE COMPENSTATION <21> <22>
When in the probe compensation mode, an external clock is supplied to the acquisition memory as data through gates
A02U252-A <22> and A02U252-B <21>. Channel 0 is used as trigger and channel 1 is used for data. The MPU
recognizes over- or under-compensation from the aquired data on channel 1. (Channel 1 is the result of the clock
compared with threshold A.) In this mode, A02U234 pin 15 <21> is set to high in order to maintain a high output level at
A02U220 <21> and A02U222 <21>.
338 A03 ACQ CONTROL BOARD <5> <6> <7>
The A03 acquisition control board (parallel data) contains two registers and memory that acquisition parameters are
loaded into before data acquisition. It also contains other circuitry that controls the trigger sequence and the acquisition
memory.
The simplified block diagrams are shown in Figures 4-16 and 4-17. Figure 4-16 shows the I/O address decoders, start
logic, clock qualify/SQRAM data register, qualify circuit, and strobe generator circuit.
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