Tektronix 2236, Instruction Manual

Page: 67 / 350

Theory of Operation— 2236 Service
Synchronizer
The Synchronizer circuitry is used for gating signals from
the Input Multiplexer and the 100 MHz reference clock to
the two count chains. It is configured under firmware control
for period or width measurements in both gated and
nongated modes. The operation of this circuit is described
below for each of the four measurement modes.
See Figure 3-6 for a simplified circuit diagram of period
measurement operation. Figures 3-7 and 3-8 show circuit
waveforms for nongated and gated measurements
respectively.
NONGATED PERIOD. In this mode, the sample counter
chain counts the number of periods of the synchronizer in­
put signal that occur while the Enable signal is LO, and the
time counter chain will count the number of periods of the
100 MHz clock during the same interval.
The Barm signal is LO and Q1006 is biased off. This
places a HI on one input of U1004A through CR1004 and
the gate output will be LO. The Enable signal is inverted by
U1006C and is passed through CR1003 and U1004C. The
D input of U1001A will therefore receive the complement of
the Enable signal.
The Width signal is LO, causing the output of U1006B to
be HI and the output of U1006A to be LO. Input pin 9 of
U1004B is driven HI by CR1002 and causes the gate output
to be LO. Also, input pin 9 of U1002A is driven LO by
CR1001 to cause the gate to function as a noninverting
buffer. The output of the Input Multiplexer drives the clock
input of U1001A, and since Q1012 is biased on by U1006A,
it also drives one input of U1003B. Transistor Q1011 is bi­
ased off by U1006B.
The reset signals Ereset and Creset always work in tan­
dem so that flip-flop U1001A can be preset by Q1010 at the
same time that flip-flop U1001B is preset.
Input pin 12 of U1003C is effectively disconnected, since
Q1011 is biased off. The Q output signal of U1001A is cou­
pled through U1003C to drive the D input of U1001B and
one input of U1003B. Transistors Q1008 and Q1009 form
an ECL-to-TTL level translator to produce the Busy signal.
When the Enable signal goes LO, the next positive tran­
sition of the synchronizer input signal will cause the Q out­
put of U1001A to go LO. The Q output of U1001B will then
go LO after the next positive transition of the 100 MHz
clock. This allows U1003B to pass an inverted version of
the synchronizer input signal and U1003C to pass an in­
verted version of the 100 MHz clock. The two count chains
both increment on each positive transition applied to them.
When the Enable signal goes HI again, the next positive
transition of the synchronizer input signal will cause the Q
output of U1001A to go HI. The Q output of U1001B will
then go HI on the next positive transition of the 100 MHz
clock. This disables U1003B and U1003C from passing their
respective signals to the count chains.
The period of the synchronizer input signal is calculated
by the firmware that divides the time count by the sample
count. To calculate frequency, the firmware divides the sam­
ple count by the time count.
GATED PERIOD. For this mode of operation, the circuitry
functions almost identically to the Nongated Period mode.
However, the measurement periods are broken up into one
or more time periods determined by the oscilloscope sweep
logic through the Delay End signal.
The measurement starts at the end of the oscilloscope
delay interval after the Enable signal has gone HI. The
Delay End signal goes LO at the end of the delay interval
and B Sweep triggering is enabled. Transistor Q1007 in­
verts the Delay End signal and applies it to pin 4 of
U1004A. The Barm signal is HI and Q1006 is biased on to
3-23
Figure 3-6. Simplified diagram of the Period measurement
circuitry.