Tektronix 2236, Instruction Manual

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Theory of Operation— 2236 Service
Buffered Data Bus Latch
The Buffered Data Bus Latch, U1409, is an 8-bit trans­
parent latch used to buffer data from the CPU that is being
sent to output ports. It is strobed by the E output of the
CPU and latches whatever data is on the CPU data bus to
provide data hold time for output operations. The latch is
socketed so that it can be removed to isolate the CPU data
bus from the output ports for troubleshooting purposes.
Counter Data Bus Switch
The Counter Data Bus switch SI 400 is an octal switch
that is used to isolate the CPU data bus from the counter
read ports. The switches are used for troubleshooting pur­
poses by isolating the counter read ports from the CPU data
bus.
DISPLAY SYSTEM
The Display system, shown on Diagram 13, consists of
decoding and latching circuitry, a filament driver, and the
display panel with its digit and segment drivers. It is used to
display measurement results and instrument status with a
nine-byte buffer area in read-write memory containing the
segment codes for the nine display digits. On every CPU
interrupt, the firmware outputs the segment code for the
next digit to be displayed.
Display Multiplexing
Display multiplexing sequentially selects the digits and
the segments to be illuminated for display on the front-panel
readout.
The digit display cycle begins with the CPU placing a LO
on all data lines. Segment latch U1506 will transfer this data
to the Q outputs when clocked by the Segment control line
so that all digit segments are blanked. The CPU then incre­
ments the digit position to be displayed and outputs this
number on the data bus. Digit latch U1504 will transfer this
digit position to the Q outputs when clocked by the Digitreg
control line. Demultiplexer U1505 will decode this number
and drive the corresponding output line HI to enable the digit
to be displayed. The CPU will then output on the data bus
the segment code for the digit to be displayed, and U1506
will latch this data when clocked again by the Segment con­
trol line.
Drivers U1507 and U1508 convert the CMOS and TTL
output levels from U1505 and U1506,respectively,to the 30-
volt signal levels necessary to drive the display. Transistors
Q1501, Q1502, and Q1503 provide level translation for the
“a” segment of the display.
Display and Filament Driver
The display panel V9900 is a vacuum-fluorescent type
and functions like a crt. The display filament (cathode) pro­
vides electrons which are accelerated by the control grid. To
turn on a digit, the control grid is raised to a potential of
about 30 volts. The segments (anodes) are coated with a
phosphor and are illuminated when their potential is also 30
volts.
The filament driver provides the ac drive for the display
filament. Since the brightness of a display digit is dependent
on the cathode-to-anode voltage, the average dc voltage at
all points on the filament must be the same (to keep the
cathode-to-anode voltage the same for all digits). This is
achieved by using a balanced push-pull driver, with the ac
drive synchronized with the display multiplexing to prevent
display flicker.
Whenever output pin 3 of U1505 goes HI to enable the
far-left digit of the display, flip-flop U1509A is toggled and
the filament drive reverses polarity. When the Q output of
U1509A is HI, Q1504 and Q1506 are biased off and Q1505
and Q1507 are biased on. This causes current flow into the
F2 terminal of V9900 and current flow out of the FI terminal.
When the flip-flop toggles into the opposite state, Q1504
and Q1506 turn on and Q1505 and Q1507 turn off, causing
filament current flow in the reverse direction.
INPUT/OUTPUT PORTS
The Input/Output ports are the blocks used by the CPU
(under firmware guidance) to control the CTM hardware, to
read counter contents and status, and to sense the front-
panel switch positions.
Sample Counter Read Ports
The Sample Counter Read Ports, shown on Diagram 11,
are three 8-bit input ports for reading the sample counter
contents and the Busy control line status and consist of tri­
state buffers U1104, U1105, U1106, and U1107. Reading
address B000 gets the least-significant byte of the sample
counter by enabling U1104 and two of the six buffers of
U1105. The middle byte is obtained by reading address
B001 and enabling the remaining four buffers of U1105 and
four buffers of U1106. The most-significant 7 bits of the
counter and the Busy control line status are obtained by
reading address B002 to enable the remaining two buffers
of U1106 and all buffers of U1107.
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