Tektronix 2236, Instruction Manual

Page: 56 / 350

Theory of Operation— 2236 Service
DS518. The output state of U502 is used in the Auto Base­
line circuit as described in the “P-P AUTO and TV FIELD”
section.
NORM. When NORM Trigger mode is selected, input pin
12 of U532D is held HI by S401B, causing the gate output
to also be HI. The output of U532C will then be LO and
U506A will not be held reset. Input pin 4 of U532A is held HI
by S401C, causing the output to be LO which places a LO
on the D input of U506A. Trigger signals received at the
clock input of U506A will then clock this LO to the Q output.
During the previous holdoff period, U506A had been set
by U532B so that the Q output went LO. This biased on
Q576 and the A Miller Sweep was prevented from running.
Whenever U506A is clocked following holdoff by a trigger
signal, the LO on the D input will be transferred to the Q
output and the Q output will go HI. This will bias off Q576
and the A Miller Sweep will generate the sweep ramp as
described in the “A Miller Sweep Generator” section. When
the ramp voltage is about 12 V, Q525 will be biased on. The
output of U532B will change from LO to HI, setting U506A
and biasing on Q576. With Q576 conducting, holdoff one-
shot U504B will be triggered and the A Miller Sweep Gen­
erator will be reset to turn off Q525.
With U504B triggered, the Q output changes from HI to
LO and will stay LO for a time duration determined by the
Var Holdoff circuitry and the A SEC/DIV switch position.
VAR HOLDOFF potentiometer R9521 determines the
amount of charging current available to charge C518, C519
or C520 at pin 15 to_the threshold voltage level on pin 14.
During the time the Q output is LO, the set input of U506A
is held HI so that no trigger pulses can initiate a new sweep.
When pinj 5 of U504B reaches the threshold voltage on pin
14, the Q output goes HI to end the holdoff period and
release U506A from the set condition. The circuit is then
enabled to generate another sweep once a trigger signal is
again applied to the clock input of U506A.
P-P AUTO and TV FIELD. When P-P Auto or TV Field is
selected, the Auto Baseline configuration is enabled. Pin 12
of U532D is held LO by R569 and the output will follow the
signal provided by the Q output of U502. If trigger signals
are being received by U502, the output of U532D will be HI
and cause the output of U532C to be LO. Flip-flop U506A
will respond to trigger signals as described in the “NORM”
section. If trigger signals are not being received by U502,
the output of U532D will be LO. The output of U532C will
then be the inverse of the input signal applied to pin 11 so
that U506A will be reset when holdoff ends, causing a
sweep to be generated. With no new trigger pulses being
applied to the circuitry, U506A will be continuously set and
then reset in this manner to generate sweeps.
SGL SWP. In the Sgl Swp Mode, both the P-P AUTO
and NORM buttons are out. This results in a LO at the out­
put of U532C so that U506A is not held reset. A LO is also
on input pin 4 of U532A.
During the previous holdoff period, U532B had reset
U506B to cause the Q output to be LO. The D input of
U506A wiHtherefore be HI and clock signals to the gate will
keep the Q output LO and the sweep disabled. When the
SGL SWP button is pushed in, the Q output of U504A will
go LO for a time period determined by the time constant of
R504 and C504 and then return HI. This HI will then clock
through the HI on the D input of U506B to the Q output.
Consequently the output of U532A will go LO and CR514
will be reverse biased to bias on Q511 and light the READY
LED. The next trigger pulse applied to the clock input of
U506A will then initiate a sweep as described previously. At
the end of the sweep, U506B will again be reset, causing
the TRIG’D LED to go out and place a HI on the D input of
U506A. A new sweep will not be initiated until the SGL SWP
button is again pushed.
X-Y. In the X-Y mode of operation, the XY line is LO
which holds the input of U532B LO through CR518. The
output of U532B will hold U506A set and no sweeps can be
initiated.
ALTERNATE B SWEEP
The Alternate B Sweep circuitry, shown on Diagram 5,
produces a linear voltage ramp that is amplified by the Hori­
zontal Amplifier to provide the B Sweep horizontal deflec­
tion on the crt. The Alternate B Sweep circuitry also
produces the sweep-switching signals that control the dis­
play of the A and B Sweeps, and the gate signals used by
the Intensity and Z-Axis circuits to establish the crt
unblanking and intensity levels needed for producing both
the A Intensified and B Sweep displays.
The B Sweep ramp is enabled by the B Sweep Logic
circuit either immediately after the end of the established
delay time (Runs After Delay) or upon receipt of the first
trigger signal after the delay tim has elapsed. This delay
time is a function of the B Delay Time Position Comparator
circuit and the A sweep.
B Miller Sweep Generator
The B Miller Sweep Generator is composed of Q709,
Q710A, Q710B, Q712, and associated timing components.
This circuit produces the B Sweep and functions in the
same manner as the A Miller Sweep Generator; see the “A
Miller Sweep Generator” section for a description of cir­
cuitry operation. The output at the collector of Q712 drives
the Horizontal Amplifier and Q643.
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