PICO-IMX6 REV. A1. HARDWARE MANUAL
– VER 1.01 – JAN 28 2016
Page
35
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3.8. PCI Express
The PICO-IMX6 is equipped with a single lane PCI Express interface, implemented in the i.MX6
processor.
The PCI Express interface complies with PCIe specification Gen 2.0 and supports the PCI Express
1.1/2.0 standards. The PCI Express module is a dual mode complex, supporting root complex operations
and endpoint operations.
PCI Express PHY Features
5 Gbps data transmission rate
Integrated PHY includes transmitter, receiver, PLL, digital core, and ESD.
Programmable RX equalization
Designed for excellent performance margin and receiver sensitivity
Robust PHY architecture tolerates wide process, voltage and temperature variations
Low-jitter PLL technology with excellent supply isolation
IEEE 1149.6 (JTAG) boundary scan
Built-in Self-Test (BIST) features for production, at-speed, testing on any digital tester
5Gb/s PCIe Gen 2 and 2.5Gb/s PCIe Gen 1.1 test modes supported
Advanced built-in diagnostics including on-chip sampling scope for easy debug
Visibility & controllability of hard macro functionality thru programmable registers in the design
Over-rides on all ASIC side inputs for easy debug
Access register space thru simple 16 bit parallel interface
Access register space thru JTAG
For additional details, please refer to the “PCI Express (PCIe)” chapter of the “i.MX6 Reference Manual”.
Table 13 - PCI Express Signal Description
PIN
CPU
BALL
CPU PAD NAME
Signal
V
I/O Description
X2_56
D7
CLK1_P
PCIEA_CLKP
2V5
O
PCI Express clock differential
pair positive signal
X2_58
C7
CLK1_N
PCIEA_CLKN
2V5
O
PCI Express clock differential
pair negative signal
X2_62
B3
PCIE_TXP
PCIEA_TXP
2V5
O
PCI Express Transmit output
differential pair positive
signal
X2_64
A3
PCIE_TXM
PCIEA_TXN
2V5
O
PCI Express Transmit output
differential pair negative
signal
X2_68
B2
PCIE_RXP
PCIEA_RXP
2V5
I
PCI Express Receive input
differential pair positive
signal
X2_70
B1
PCIE_RXM
PCIEA_RXN
2V5
I
PCI Express Receive input
differential pair negative
signal
NOTE: The PCIE_TX pair has decoupling capacitors on the PICO Compute Module valued 10nF
