MST9E19A
SXGA/WXGA+ LCD TV Controller with Video Decoder & 10-bit Dual LVDS Transmitter
Preliminary Data Sheet Version 0.1
Version 0.1
5/19/2006
Copyright © 2006 MStar Semiconductor, Inc.
All rights reserved.
PIN DIAGRAM (MST9E19A)
Pin 1
1
2
3
4
5
7
9
11
13
14
17
18
21
23
25
27
28
30
32
34
36
39
41
43
6
8
10
12
15
16
19
20
22
24
26
29
31
33
35
37
38
40
42
44
45
46
47
48
50
51
52
49
156
155
154
153
152
150
148
146
144
143
140
139
136
134
132
130
129
127
125
123
121
118
116
114
151
149
147
145
142
141
138
137
135
133
131
128
126
124
122
120
119
117
115
113
112
111
110
109
107
106
105
108
DIGO[8]
GND
AVDD_MEMPLL
PWM3
PWM2
DIGO[9]
DIGO[7]
DIGO[5]
DIGO[3]
DIGO[1]
VDDC
VDDP
PWM_SENSE
DIGO[6]
DIGO[4]
DIGO[2]
DIGO[0]
GND
PWM_DRV
PWM_FB
IRIN
INT
PWM1
PWM0
GND
VDDP
ALE
RDZ
WRZ
VDDC
GND
VDDP
RXCKP
GND
RX0N
RX0P
AVDD_DVI
RX1N
RX1P
RX2P
REXT
DDCD_CK
VSYNC1
VCLAMP
REFM
BIN1M
GND
RX2N
AVDD_DVI
DDCD_DA
HSYNC1
RMID
REFP
BIN1P
SOGIN1
GIN1P
GIN1M
RIN1P
RIN1M
BIN0M
BIN0P
GIN0M
GIN0P
SOGIN0
RIN0M
RIN0P
HSYNC0
VSYNC0
RXCKN
AVDD_ADC
GND
C1
Y1
C0
Y0
CVBS2
CVBS1
VCOM1
CVBS0
VCOM0
CVBSOUT
GND
VCOM2
CVBS3
AD[7]
AD[6]
AD[5]
AD[4]
AD[3]
AD[2]
AD[1]
AD[0]
SDO
CSZ
SDI
SCK
SAR3
SAR1
SAR2
SAR0
DDCA_CK
DDCR_CK
DDCA_DA
DDCR_DA
