Tadpole SPARCbook 3 series, Reference Manual

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11-28
Display Interface
RAMDAC
11.4.3 Color palette accesses
The RAMDAC contains three 256 x 8 bit color lookup tables (palettes)
which are accessed as a single 256 x 24 bit palette via an internal control
mechanism. Before reading from the palette, the Palette Address (Read
Mode) register must be written to specify the starting address. Conversely,
the Palette Address (Write Mode) must be written before writting to the
palette. It should be noted that writing to either Palette Address register
changes the contents of both.
The RAMDAC contains address counters which simplify palette accesses
by keeping track of access cycles. The first counter is reset to zero
whenever either Palette Address Register is written to and incremented
each time an access to the color lookup table is made. The second address
count increments the address register after each access to the blue entry.
This is illustrated in Figure 6-8.
For example, to write a new set of color information to the main palette
would require the following steps.
First, an initial value is written to the Palette Address (Write Mode) address
register at 0x38000200 to specify the first location in the color palette to be
accessed. Next, a byte of red color information is written to the Palette Data
location at 0x38000208 followed by a green byte, followed by a blue byte.
The RAMDAC transfers all 24 bits of color information into the addressed
Figure 11-6 Multiple Access Support
RED
(First Access)
GREEN
(Second Access)
BLUE
(Third Access)
Address Register = n
Address Register = n+1
Address Register = n+2
RED
(Fourth Access)
RED
(Seventh Access)
GREEN
(Fifth Access)
GREEN
(Eighth Access)
BLUE
(Sixth Access)
BLUE
(Ninth Access)
S3GX_TRMBook Page 28 Friday, September 19, 1997 11:39 am