Tadpole SPARCbook 3 series, Reference Manual

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10-2
Parallel Interface
Parallel Port Overview
10.1 Parallel Port Overview
The parallel port of the MACIO comprises four 8-bit port registers, three
16-bit configuration registers and a 64 byte FIFO. Parallel communications
can be carried out using programmed I/O or DMA operations; the
MACIO’s internal DMA controller provides the necessary hardware
support.
The direction, timing and protocol are programmable to support the wide
variety of Centronics interfaces on peripheral devices.
Connection to the parallel interface on the SPARCbook is made via the
supplied parallel breakout cable, which makes available a standard 25 way
D-type connector. Pinout details for this connector are provided in
Appendix B.
10.1.1 Parallel Port DMA Operations
The parallel port DMA can operate in either chained or unchained transfer
mode. Mode selection, interrupt control and DMA control are carried out
via the Parallel Port Control Register (P_CSR). The direction of transfer is
controlled via the Parallel Port Transfer Register (P_TCR), and is reflected
in the P_CSR.
Unchained Mode
In the unchained transfer mode, a single address register and byte counter
are used. The byte counter is enabled via the P_CSR and decrements each
time a byte is transferred. When the byte counter expires (from 0x1 to 0),
bit 9 in the P_CSR becomes set and an interrupt generated. Unchained
DMA transfers terminate in two ways: either when the byte counter expires,
or when software clears bit 9 in the P_CSR.
Chained Mode
Chained DMA transfers use two additional registers to control operations.
These are the NEXT Address Register and NEXT Byte Count Register. The
NEXT registers provide a new address and byte count for the next DMA
operation in a sequence of operations. Chaining is enabled via bits13 and
24 in the P_CSR. When the byte counter expires in the chained mode, the
contents of the NEXT registers are transferred into the corresponding
address and byte count registers.
The NEXT registers are located at the same addresses as their current
counterparts, and can be accessed only when bit 24 in the P_CSR is set.
The NEXT registers need to be updated before the current byte count
expires in order for the DMA controller to load valid contents into the
address and byte counter registers. However, the NEXT Byte Counter does
not need to be reprogrammed for each DMA operation when setting up a
S3GX_TRMBook Page 2 Friday, September 19, 1997 11:39 am