Tadiran Telecom Coral IPx 500, Installation Manual

Page: 443 / 544

Shared Service Ports
9-15
IPx 50
0M Ba
ckpla
ne Main
Service Boar
d i
n
side t
h
e IPx 50
0M Cag
e
9
0
Figure 9-1
illustrates the HDC PROM (U107) location on the MSBipx card.
Figure 9-5
illustrates the four major circuit areas of the HDC circuitry in a block diagram.
The HDC serves as a communication link between the MCP-IPx and the peripheral
cards. The HDC includes four distinct spatially divided functions:
„
External Synchronization (ES) circuit
„
Digital tone generators (dial, busy, ringing, ringback, DTMF, MFC, and test;
programmed on U118 PROM)
„
High-Level Data Link Control (HDLC) bus drive circuitry
„
Pulse Code Modulation (PCM) bus drive circuitry with a matrix for 512 timeslot
switching calls
Figure 9-5 HDC Circuit
Block Diagram
Clock Selection
The external clock selector monitors the two inputs for the presence of an 8.0 kilohertz
(kHz) clock signal that may be obtained from the incoming data stream of a digital
trunk card. A primary and secondary clock source may be defined in the system
7 HDC (U107) High Density Control
Digital Tone Generation
CPU
Universal I/O Slots
Clock & Sync Generation
External Clock Selector
Primary
Sync Secondary
Sync
HDLC
PCM
HDLC Tx
PCM Tx
HDLC Rx
PCM Rx
Timeslots
0 - 511
Clock (4.096 MHz)
Sync (8 KHz)
Clk Select
RAM
HDC
Software
PROM
U107
Local
Bus
Data
Time Slot Management
512 x 512