117
ARC CPU Address Decoder Registers
DesignWare ARC AXC003 CPU Card User Guide
Version 6323-018
Synopsys, Inc.
May 2017
31:1
Reserved
R
0x0*
9.3 ARC CPU Address Decoder Registers
The ARC CPU Address Decoder Registers are re-programmed by the pre-bootloader. The
reset values mentioned here are the reset values prior to running the pre-bootloader. See the
Example Register Settings for the Default Memory Map
on page 69 for the register settings
after the pre-bootloader runs.
CPU_A_SLV0: ARC CPU Slave Select Register 0
Address offset:
0x1020
Reset value:
0x0000_5322
Table 6
CPU_A_SLV0 Register
Legend: * reset value
Bit
Name
Access Value Description
3:0
SLV_SEL0
RW
Slave select for address aperture[0]
0
no slave selected
1
slave 1 selected (=> DDR controller)
2*
slave 2 selected (=> SRAM controller)
3
slave 3 selected (=> AXI tunnel)
4
slave 4 selected (=> AXI2APB bridge)
5
slave 5 selected (=> ROM Controller)
6
slave 6 selected (=> IOC port)
7
Reserved
7:4
SLV_SEL1
RW
2*
Slave select for address aperture[1]
1)
11:8
SLV_SEL2
RW
3*
Slave select for address aperture[2]
1)
15:12
SLV_SEL3
RW
5*
Slave select for address aperture[3]
1)
19:16
SLV_SEL4
RW
0*
Slave select for address aperture[4]
1)
23:20
SLV_SEL5
RW
0*
Slave select for address aperture[5]
1)
27:24
SLV_SEL6
RW
0*
Slave select for address aperture[6]
1)
31:28
SLV_SEL7
RW
0*
Slave select for address aperture[7]
1)
1) Same encoding as SLV_SEL0
CPU_A_SLV1: ARC CPU Slave Select Register 1
Address offset:
0x1024
Reset value:
0x4330_1111