CHAPTER FOUR
The input signal is AC coupled by C143 through R149 to attenuator FET Q4. Q4 is employed as
a voltage controlled resistor to maintain a constant level at the input of U48 of approximately 13
mV Peak-to-Peak. It is not recommended to observe this signal. U48 provides a gain of 14
yielding about 180 mV Peak-to-Peak at U46-13 and the FILT INPUT [9]. U46 is an Analog
Switch. U46, pins 1, 2, 10 and 15, are used to provide signal inversion by controlling whether the
Plus or Minus input at U47 is driven. The input of U46 at pin 15 comes from the output of U41
pin 6 [9]. U47 provides a gain of about 9 so that the AGC signal is a constant 2 Volts Peak-to-
peak at TP2.
Analog Switch, U46 pins 12, 13, and 14 are used to route the code (C) to the input of amplifier
U41 [9] when the Envelope Filter is not used (OFF).
Completing the AGC loop, U44, pins 15, 16, and 13 are controlled by comparing AGC with –
1V. When the negative peak of AGC exceeds –1V, Q3 supplies current to C141, which raises the
voltage at the gate of FET Q4, lowering its resistance and decreasing the input to U48. When Q3
is not conducting R137 pulls C141 minus increasing the resistance of Q4. R140 provides fast
recovery when loss of activity is detected at AS1 (Activity Sensor 1). The AGC signal is applied
to the output buffer U54 and to the
∅
B and
∅
C detectors U44 pin 7, and U44 pin 9.
∅
B
detector, U44 pins 7, 8, and 5, is a zero crossing detector with hysteresis on the negative edge.
The positive (on-time) edge coincides with the positive zero crossing of the input code.
∅
C
detector U44, pins 9, 10, and 12, detects the Mark Amplitude cycles of the input code.
∅
B and
∅
C are used by the decoders which are located in U23
∅
C is also used by the activity sensing
circuitry described above. A secondary function of the activity sensor is to increase the threshold
of the
∅
C detector at pin 10 slightly to provide hysteresis for AS1.
Shown in the lower left of this logic is the LOS (Loss of Signal) circuitry U44 pin 4. This circuit
senses peak amplitudes of the input signal versus an adjustable threshold established by
potentiometer R135 (THOLD).
4.9
[8] STCG (TRANSLATOR
μ
P
)
This logic contains the heart of the Translator: The Microprocessor-Controller (U32), the ROM
(U27) - program storage, and the RAM (U28) - variable storage. Also included are the VIA’s
for communications and decoding.
The Microprocessor is an 8 bit CMOS device. It accepts as an input clock
∅
2-IN and outputs
∅
2.
Other inputs are the non-maskable interrupt (NMI/), the maskable interrupt (IRQ), and RESET
(RES/). The data lines (D0-D7) are bi-directional. The address lines (A0-A15) are outputs. The
ROM contains the program, which the Microprocessor executes. When an address of 8000 Hex
or more is on the address bus, the ROM outputs to the data bus while
∅
2 is high.
The RAM is used for temporary storage of data and variables. The RAM is disabled for all
addresses above 007F Hex by U23 as the addresses are used by the VIA’s and ROM.
4-12
TM7000 TymMachine TCG/T (Rev D)
Symmetricom, Inc.
