Super PDSMi, User Manual, Page: 61 / 100

Chapter 4: BIOS
4-13
Adjacent Cache Line Prefetch
The CPU fetches the cache line for 64 bytes if this option is set to Disabled. The
CPU fetches both cache lines for 128 bytes as comprised if Enabled. The options
are Disabled and Enabled .
VT Feature
( * Available when supported by the CPU.)
Set to Enabled to utilize enhanced virtualization capabilities provided by the
Intel Vanderpool Technology which allows one platform to run multiple operat-
ing systems and applications in independent partitions, creating multiple "virtual"
systems in one physical computer. The options are Enabled and Disabled .
( *Note: If there is any change to this setting, you will need to power off and re-
start the system for the change to take effect.) Please refer to Intel’s web site
for detailed information.
C1 Enhanced Mode
( * Available when supported by the CPU.)
Set to Enabled to enable the function of Enhanced Halt State to lower CPU
voltage/frequency to prevent overheat. The options are Enabled and Disabled.
( *Note: please refer to Intel’s web site for detailed information.)
No Execute Mode Memory Protection
Set to Enabled to enable Execute Disable Bit and allow the processor to classify
areas in memory where an application code can execute and where it cannot, and
thus preventing a worm or a virus from inserting and creating a fl ood of codes to
overwhelm the processor or damage the system during an attack.
(*Note: this feature is available when your OS and your CPU support the function
of Execute Disable Bit.) The options are Disabled and Enabled . (Note: For more
information regarding hardware/software support for this function, please refer to
Intel's and Microsoft's web sites.)
Processor Power Management
( * Available when supported by the CPU.)
This feature allows the user to determine the processor power management
mode. The options are Disabled and C States Only. If set to Disabled, C States
and GV1/GV3 are disabled. If set to C States only, the processor power will be
controlled through CPU power states in the APCI setting.