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Sundance Spas SMT398, User Manual

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Sundance Spas SMT398 User Manual Download Page 18

Version 1.1.1 

Page 18 of 38 

SMT398 User Manual 

 

 

JTAG/Boundary Scan 

JTAG Programmer (iMPACT) 

The JTAG Programmer software is a standard feature of the Alliance Series ™ and 
Foundation Series ™ software packages. JTAG Programmer is a part of Web Pack, 
which can be downloaded from the following site: 

Xilinx JTAG programmer

 

 

 

Configuring with the parallel cable III or IV 

The JTAG chain is composed of the CPLD and the FPGA. 
The CPLD is pre-programmed by Sundance.  

Do NOT try to reprogram the CPLD without SUNDANCE approval 

 
 
 
 
 
 
 
 
 
 
 

Figure 5: JTAG Chain on the SMT398 

 
When accessing the board using JTAG, the CPLD can be bypassed and you can 
configure the FPGA only. 
Xilinx describe how to connect both download cables at: 

Parallel cables

 

Xilinx describe how to configure their devices using these cables at: 

Configuration 

Mode General Information

. 

For complementary and more detailed information please go to: 

Xilinx 5 software 

Manuals and Help

. 

See board header pinout in 

Table 9: Connector J13-JTAG Header 

Summary of Contents for SMT398

Page 1: ...SMT398 User Manual...

Page 2: ...Page 2 of 38 SMT398 User Manual Revision History Date Comments Engineer Version 18 07 03 First released version E P 1 0 0 22 08 03 TIM CONFIG signal feature described E P 1 1 0 27 08 03 Minor correcti...

Page 3: ...Installation 8 SMT398 Alone 8 SMT398 DSP TIM 9 FPGA Configuration 10 Electrical Interface 10 The service CPLD 10 CPLD Functions 11 Virtex II Bitstream Format 14 Bitstream Re formatting 15 CPLD code v...

Page 4: ...29 Review Procedures 29 Validation Procedures 29 Circuit Diagrams 29 Ordering information 29 Full configuration 30 Basic configuration 31 Memories 31 SHBs 31 ComPorts 31 Global Bus 31 External Clock 3...

Page 5: ...mensions in inches 28 Figure 10 SMT398 Components placement Top view 32 Figure 11 SMT398 Components placement Bottom view 33 Figure 12 Top View QSH 30 34 Figure 13 Top View of JTAG Multilinx headers 3...

Page 6: ...398 User Manual Physical Properties Dimensions See Physical specifications of TI TIM specification user s guide Weight Varies in function of board configuration Supply Voltages See Power Supplies Supp...

Page 7: ...78 I O pins 183 I O pins 16 bit data FPGA Virtex II FF896 1152 XC2V1000 XC2V8000 432 to 824 I O Pins 1 5V Core 1 5V 3 3V I O 2 4 8 or 16Mbytes ZBT RAM as SMT358 Xilinx XC95288 CS280 CPLD on Comm Port...

Page 8: ...3v compatible carrier boards plugged in a host computer PC PCI VME carrier etc like SMT310Q SMT328 SMT300 etc Please follow these steps to install the SMT398 module on a Host system 1 Remove the carr...

Page 9: ...rocessor board to handle the interactions with the Host by software instead of having to implement a communication interface in the SMT398 FPGA Global Bus interface or ComPort interface on ComPort 3 F...

Page 10: ...in depth understanding of the configuration sequence and of the Virtex II However for the purpose of debugging and designing for the SMT398 an overview of the necessary configuration protocol and bit...

Page 11: ...8 SMT398 User Manual Figure 2 FPGA configuration in SelectMap mode using CPLD CPLD Functions Decode Commands coming on ComPort 3 To Implement a ComPort Receiver on ComPort 3 after Reset or at Power up...

Page 12: ...starting with the least significant byte LSByte i e byte0 as shown in Figure 3 ComPort word Byte order and 1 byte at a time Byte3 Byte2 Byte1 Byte0 31 24 23 16 15 8 7 0 D31D30D29D28D27D26D25D24D23D22...

Page 13: ...set control over the FPGA At power up or on reception of a low TIM global Reset pulse the CPLD drives the FPGAResetn signal low and keeps it low When the ENDKEY has been received the CPLD drives FPGAR...

Page 14: ...nning and can t be interrupted by a global Reset pulse when the FPGA needs to be configured with a new bitstream Notes TIM CONFIG is only available on SMT398 v3 The SMT398 version is written on TOP of...

Page 15: ...ode versions V1 0 Initial release that only receives the bitstream and configures the FPGA FPGAResetn is NOT implemented and ComPort 3 is NOT released once the FPGA is configured V2 0 Indicated on a s...

Page 16: ...48 48 864 8 XC2V2000 2M 56x48 10 752 336 56 56 1 008 8 XC2V3000 3M 64x56 14 336 448 96 96 1 728 12 XC2V4000 4M 80x72 23 040 720 120 120 2 160 12 XC2V6000 6M 96x88 33 792 1 056 144 144 2 592 12 XC2V800...

Page 17: ...are can be developed to communicate with the SMT398 See SMT6025 User Manual on Sundance Web site for more information on how to develop Host applications for Sundance Hardware The host Software applic...

Page 18: ...the CPLD and the FPGA The CPLD is pre programmed by Sundance Do NOT try to reprogram the CPLD without SUNDANCE approval Figure 5 JTAG Chain on the SMT398 When accessing the board using JTAG the CPLD...

Page 19: ...he CPLD is dedicated to control the FPGA and does not provide a communication channel to user logic residing on the FPGA anymore The CPLD is connected to ComPort number 3 of the SMT398 connector which...

Page 20: ...e chip enables are available on each bank for simple depth expansion with no data contention Each bank is composed of one chip available in 4 different sizes as presented in Table 2 ZBTRAM sizes For m...

Page 21: ...a Rate Up to 8 Mbytes of QDR Quad Data Rate Synchronous Pipelined Burst SRAMs memory is provided with direct access to the FPGA Provision has been made to accommodate up to 64 Mbytes of QDR when the m...

Page 22: ...vailable in 3 different sizes up to 164Mbits chips are expected QDR part number Size in bits Size in Bytes Actual Memory size Amount of memory per board CY7C1302V25 8Mb 1MBytes 512kx18 2 MBytes k7q163...

Page 23: ...are connected on the TIM They are guaranteed for a transfer rate of 20MB s which could lead using the 6 ComPorts available to a 120MB s transfer rate The ComPort drives at 3 3v signal levels FPGA Vir...

Page 24: ...See Sundance SDB specification The bigger the FPGA the more pins from the SHB Connector become available Features High speed socket strip QSH 030 01 L D A K on the SMT398 mates with QTH 030 01 L D A...

Page 25: ...to communicate with other Sundance TIM modules you can implement a 16 bit SHB interface sitting on 25 pins of an SHB connector Then the SHBs are parallel communication links for synchronous transmissi...

Page 26: ...the external device writes data across the global bus to the FPGA Clocks An on board oscillator provides a free running clock to the FPGA and CPLD The default is a 50Mhz oscillator but other frequenc...

Page 27: ...u analyse the total FPGA device power drawn by using Xilinx XPOWER before implementing your design in the FPGA This will tell you if you need to use the external power connector provided on our carrie...

Page 28: ...e QDR core voltage is provided through an adjustable linear voltage regulator from 3 3V Fan A fan coupled with a heatsink can be mounted on the Virtex II to provide heat dissipation but a permanent ai...

Page 29: ...rried out as indicated in design quality document QCF14 and in accordance with Sundance s ISO9000 procedures Validation Procedures The validation procedure is happening during the verification procedu...

Page 30: ...igurations options are highlighted in blue in Table 6 SMT398 V3000 4 Zx Qy Board Type Virtex II part Virtex II speed grade On board ZBTSRAM in MBytes On board QDRSRAM in MBytes Virtex II SMT398 XC2V30...

Page 31: ...25 I Os per SHB connectors are available to allow the implementation of up to 4x16 bit SDB interfaces ComPorts 5 ComPorts are available with one ComPort 3 reserved for the FPGA configuration remains n...

Page 32: ...Version 1 1 1 Page 32 of 38 SMT398 User Manual PCB Layout Details Components placement Figure 10 SMT398 Components placement Top view...

Page 33: ...SMT398 Components placement Bottom view U1 Xilinx FPGA U2 Xilinx CPLD U3 ZBTRAM Bank1 U4 ZBTRAM Bank2 U5 ZBTRAM Bank3 U6 ZBTRAM Bank4 U10 QDR Bank1 U11 QDR Bank2 These 2 Banks share the same address l...

Page 34: ...Version 1 1 1 Page 34 of 38 SMT398 User Manual Headers Pinout SHB Header Pin2 Integral Ground plane Pin 1 Alignment Pin Blade and Beam Design 0 5 m m Figure 12 Top View QSH 30...

Page 35: ...0 B0 ACK 12 42 D20 D4 D4 D11 D11 CLK 13 43 D21 D5 D5 D12 D12 D0 14 44 D22 D6 D6 D13 D13 D1 15 45 D23 D7 D7 D14 D14 D2 16 46 D24 D8 WEN D15 D15 D3 17 47 D25 D9 REQ USERDEF0 D4 18 48 D26 D10 B3 ACK USER...

Page 36: ...Supplies VCC 3 3V 10 mA typically to the cable To target system VCC GND 4 Ground Supplies ground reference to the cable To target system ground TCK 9 Test Clock This clock drives the test logic for al...

Page 37: ...ault clock for readback operation DONE D P 8 Done Program Indicates that configuration loading is complete and that the start up sequence is in progress PROG 12 Program A Low indicates the device is c...

Page 38: ...high READ and an active low WRITE control signal to the Virtex FPGA RDY BUSY 15 Busy Pin Busy pin on the Virtex Table 11 Connector J12 Flying Lead Sets 3 4 Safety This module presents no hazard to the...

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