Sun Microsystems Netra CP3060, User Manual

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Chapter 5 Hardware and Functional Descriptions 5-15
will generate a hot-plug event to the OS. When the OS has quiesced the driver
operating the AMC module, the driver responds by writing to a CSR in the PCI-E
switch that causes de-assertion of the
HP_PWR_LED
output pin. This signal is
monitored by IPMC. When de-asserted, the IPMC informs the module to light the
blue LED, then turns off payload power, and finally turns off management power.
Clock Synchronization
The Sun Netra CP3060 blade server routes the clock synchronization signals from
the midplane (CLK1A/1B, CLK2A/2B) to the AMC slot connector CLK1 and CLK2
pins. The control of which clock signal (CLK1A or CLK1B and CLK2A or CLK2B) is
routed to the corresponding CLK1 and CLK2 pins is handled by IPMC.
FIGURE 5-5
Clock Synchronization
5.1.4.6 Southbridge
The PCI-E-based Southbridge, when used in a PC system, implements virtually a
complete desktop I/O subsystem, including Ethernet. Although many of the Super
I/O functions built into the Southbridge are not used, functional blocks of the device
CLK1+
CLK1A+
CLK1A-
CLK1B+
CLK1B-
Z2
AMC connector
CLK2A+
CLK2A-
CLK2B+
CLK2B-
Trans
Mux
(MVLDS)
Trans
Mux
(MVLDS)
CLK1-
CLK2+
CLK2_SEL
(to IPMC)
CLK2-