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© SUMMIT MICROELECTRONICS, Inc.  2001   •   300 Orchard City Drive, Suite 131   •   Campbell, CA 95008   •   Telephone  408-378-6461   •   Fax  408-378-6586   •   www.summitmicro.com

1

S93WD462/S93WD463

Characteristics subject to change without notice

Precision Supply-Voltage Monitor and Reset Controller
With a Watchdog Timer and 1k-bit Microwire Memory

SUMMIT

MICROELECTRONICS, Inc.

2029  2.2  1/23/01

FEATURES

Precision Monitor & RESET Controller

— RESET and RESET Outputs
— Guaranteed RESET Assertion to V

CC

 = 1V

— 150ms Reset Pulse Width
— Internal 1.26V Reference with ±1% Accuracy
— ZERO External Components Required

Watchdog Timer

— Nominal 1.6 Second Time-out Period
— Reset by Any Transition of CS

Memory

— 1K-bit Microwire Memory
— S93WD462

– Internally Ties ORG Low
– 100% Compatible With all 8-bit

Implementations

– Sixteen Byte Page Write Capability

— S93WD463

– Internally Ties ORG High
– 100% Compatible With all 16-bit

Implementations

– Eight Word Page Write Capability

OVERVIEW

The S93WD462 and S93WD463 are precision power
supervisory circuits providing both active high and
active low reset output. Both devices also incorporate a
watchdog timer with a nominal time-out value of 1.6
seconds.

Both devices have 1k-bits of E

2

PROM memory that is

accessible via the industry standard microwire bus. The
S93WD462 is configured with an internal ORG pin tied
low providing a 8-bit byte organization and the
S93WD463 is configured with an internal ORG pin tied
high providing a 16-bit word organization. Both the
S93WD462 and S93WD463 have page write capabil-
ity. The devices are designed for a minimum 100,000
program/erase cycles and have data retention in ex-
cess of 100 years.

BLOCK DIAGRAM

+

GND

VCC

8

5

RESET#

6

VTRIP

RESET
PULSE

GENERATOR

5kHz

OSCILLATOR

RESET

CONTROL

MODE

DECODE

ADDRESS

DECODER

WRITE

CONTROL

DATA I/O

E2PROM

MEMORY

ARRAY

RESET

7

1.26V

SK

2

DI

3

WATCHDOG

TIMER

CS

1

2029 T BD 2.0

DO

4

Summary of Contents for S93WD462

Page 1: ...Ties ORG High 100 Compatible With all 16 bit Implementations Eight Word Page Write Capability OVERVIEW The S93WD462 and S93WD463 are precision power supervisory circuits providing both active high and active low reset output Both devices also incorporate a watchdog timer with a nominal time out value of 1 6 seconds Both devices have 1k bits of E2PROM memory that is accessibleviatheindustrystandard...

Page 2: ...tender circuit Itshouldbenotedtheresetoutputsareopendrain When used as outputs driving a circuit they need to be either tied high RESET or tied to ground RESET through the use of pull up or pull down resistors Refer to the applications aid section for help in determining the value of resistor to be used Internally these pins are weakly pulled up RESET and pulled down RESET there fore if the signal...

Page 3: ... Read Upon receiving a READ command and an address clocked into the DI pin the DO pin of the S93WD462 WD463 will come out of the high impedance state and will first output an initial dummy zero bit then begin shifting out the data addressed MSB first The output databitswilltoggleontherisingedgeoftheSKclockand are stable after the specified time delay tPD0 or tPD1 Write After receiving a WRITE comm...

Page 4: ...ata to be written The host can then continue clocking in 16 bit words of data with each word to be written to the next higher address Internally the address pointer is incremented after receiving each group of sixteen clocks however once the address counter reaches xxx x111 it will roll over to xx x000 with the next clock After the last bit is clockedinnointernalwriteoperationwilloccuruntilCS is b...

Page 5: ... 1 AN AN 1 A0 DN D0 BUSY READY STATUS VERIFY tSV tHZ tEW SK 2029 ILL6 0 CS DI DO STANDBY HIGH Z HIGH Z 1 AN AN 1 BUSY READY STATUS VERIFY tSV tHZ tEW tCS 1 1 A0 Figure 3 Write Instruction Timing Figure 4 Erase Instruction Timing Figure 5 EWEN EWDS Instruction Timing SK 2029 Fig05 CS DI STANDBY 1 0 0 ENABLE 11 DISABLE 00 ...

Page 6: ...01 A6 A0 A5 A0 D7 D0 D15 D0 Write Address AN A0 EWEN 1 00 11xxxxx 11xxxx Write Enable EWDS 1 00 00xxxxx 00xxxx Write Disable ERAL 1 00 10xxxxx 10xxxx Clear All Addresses WRAL 1 00 01xxxxx 01xxxx D7 D0 D15 D0 Write All Addresses 2029 PGM T5 0 Figure 6 ERAL Instruction Timing SK 2029 ILL 8 0 CS DI DO tCS HIGH Z HIGH Z 1 0 1 BUSY READY STATUS VERIFY tSV tHZ t EW 0 0 STANDBY SK 2029 ILL 10 0 CS DI DO ...

Page 7: ...hange that affects the parameter 4 Latch up protection is provided for stresses up to 100 mA on address and data pins from 1V to VCC 1V D C OPERATING CHARACTERISTICS over recommended operating conditions unless otherwise specified Limits Symbol Parameter Min Typ Max Units Test Conditions ICC Power Supply Current 3 mA DI 0 0V fSK 1MHz Operating VCC 5 0V CS 5 0V Output Open ISB Power Supply Current ...

Page 8: ... CS Low Time 0 5 0 25 µs tSKHI Minimum SK High Time 0 5 0 25 µs tSKLOW Minimum SK Low Time 0 5 0 25 µs tSV Output Delay to Status Valid 0 5 0 25 µs CL 100pF SKMAX Maximum Clock Frequency DC 500 DC 1000 KHZ Note 1 This parameter is tested initially and after a design or process change that affects the parameter Note 1 This parameter is tested initially and after a design or process change that affe...

Page 9: ...eset Trip Point 2 55 2 7 4 25 4 5 4 50 4 75 V tPURST Power Up Reset Timeout 130 270 130 270 130 270 ms tRPD VTRIP to RESET Output Delay 5 5 5 µs VRVALID RESET Output Valid 1 1 1 V tGLITCH Glitch Reject Pulse Width 30 30 30 ns VOLRS RESET Output Low Voltage IOL 1mA 0 4 0 4 0 4 V VOHRS RESET Output High IOH VCC 75 VCC 75 VCC 75 V 2029 PGM T1 0 VCC VRVALID VTRIP tPURST RESET RESET 2029 T fig08 2 0 tG...

Page 10: ...0 10 0 25 0 016 0 050 0 40 1 27 45º 0 010 0 020 0 25 0 50 0 228 0 244 5 80 6 20 Ref JEDEC MS 012 Inches Millimeters PIN 1 INDICATOR 015 381 100 2 54 0 014 0 022 0 36 0 56 SEATING PLANE 0 008 0 014 0 20 0 36 8 Pin PDIP 0 300 0 325 7 62 8 25 0 43 10 9 MAX 0 21 5 33 MAX 0 115 0 195 2 92 4 95 0 115 0 195 2 92 4 95 Min 1 0 24 0 28 6 1 7 1 0 355 0 400 9 02 10 2 0 045 0 070 1 14 1 78 Ref JEDEC MS 001 Inc...

Page 11: ...below shows the basic timing characteristics under the assumption the reset input is shorter in duration than tPURST The same reset output affect can be attained by using the active high reset input When planning your resistor pull up and pull down values use the following chart to help determine min resistances Condition Min Typ Max Units VCC 1 0V IOL 100µA 0 3 V VCC 1 2V IOL 100µA 0 3 V VCC 3 0V...

Page 12: ...the device is still busy with the internal write If it is high the write operation has completed For the polling routine the host has the option of toggling CS for each test of DO or it can place CS high and then intermittently test DO SK is not required for any of these operations Once the device is ready it will continue to drive DO high whenever the S93WD462 WD463 is selected The ready state of...

Page 13: ...e T Tape Reel A 4 5V to 5 5V VTRIP min 4 25V B 4 5V to 5 5V VTRIP min 4 50V 2 7 2 7V to 5 5V VTRIP min 2 55V S93WD462 P A T Base Part Number Package P 8 lead PDIP S 8 lead 150mil SOIC S93WD462 8 bit configuration S93WD463 16 bit configuration Tape Reel Option Operating Voltage Range 2029 Tree 2 0 ...

Page 14: ...has been carefully checked SUMMIT Microelectronics Inc shall not be liable for any damages arising as a result of any error or omission SUMMIT Microelectronics Inc does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their...

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