STMicroelectronics STM32L151CCT6 Manual Download Page 1 | Manualshive

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This is information on a product in full production.

March 2015

DocID022799 Rev 10

STM32L15xCC STM32L15xRC

STM32L15xUC STM32L15xVC

Ultra-low-power 32-bit MCU ARM

®

-based Cortex

®

-M3,

256KB Flash, 32KB SRAM, 8KB EEPROM, LCD, USB, ADC, DAC

Datasheet

-

production data

Features

•

Ultra-low-power platform
– 1.65 V to 3.6 V power supply
–

-40 °C to 105 °C

temperature range

– 0.29µA Standby mode (3 wakeup pins)
–

1.15 µA Standby mode + RTC

– 0.44 µA Stop mode (16 wakeup lines)
– 1.4 µA Stop mode + RTC
– 8.6 µA Low-power run mode
– 185 µA/MHz Run mode
– 10 nA ultra-low I/O leakage
– 8 µs wakeup time

•

Core: ARM

®

Cortex

®

-M3 32-bit CPU

– From 32 kHz up to 32 MHz max
– 1.25 DMIPS/MHz (Dhrystone 2.1)
– Memory protection unit

•

Reset and supply management
– Low-power, ultrasafe BOR (brownout reset)

with 5 selectable thresholds

– Ultra-low-power POR/PDR
– Programmable voltage detector (PVD)

•

Clock sources
– 1 to 24 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– High Speed Internal 16 MHz

factory-trimmed RC (+/- 1%)

– Internal Low-power 37 kHz RC
– Internal multispeed low-power 65 kHz to

4.2 MHz PLL for CPU clock and USB
(48 MHz)

•

Pre-programmed bootloader
– USB and USART supported

•

Development support
– Serial wire debug supported
– JTAG and trace supported

•

Up to 83 fast I/Os (70 I/Os 5V tolerant), all
mappable on 16 external interrupt vectors

•

Memories
– 256 KB Flash memory with ECC
– 32 KB RAM
– 8 KB of true EEPROM with ECC
– 128 Byte backup register

•

LCD Driver (except STM32L151xC devices) up

to 8x40 segments, contrast adjustment,

blinking mode, step-up converter

•

Rich analog peripherals (down to 1.8 V)
– 2x operational amplifiers
– 12-bit ADC 1Msps up to 25 channels
– 12-bit DAC 2 channels with output buffers
– 2x ultra-low-power-comparators

(window mode and wake up capability)

•

DMA controller 12x channels

•

9x peripheral communication interfaces
– 1x USB 2.0 (internal 48 MHz PLL)
– 3x USART
– 3x SPI 16 Mbits/s (2x SPI with I2S)
– 2x I2C (SMBus/PMBus)

•

11x timers: 1x 32-bit, 6x 16-bit with up to 4

IC/OC/PWM channels, 2x 16-bit basic timers,

2x watchdog timers (independent and window)

•

Up to 23 capacitive sensing channels

•

CRC calculation unit, 96-bit unique ID

Table 1. Device summary

Reference

Part number

STM32L151CC

STM32L151RC

(1)

STM32L151UC

STM32L151VC

1.

For sales types ending with “A” and STM32L15xxC products

in WLCSP64 package, please refer to STM32L15xxC/C-A

datasheets.

STM32L151CCT6, STM32L151CCU6

STM32L151RCT6

STM32L151UCY6

STM32L151VCT6, STM32L151VCH6

STM32L152CC

STM32L152RC

STM32L152UC

STM32L152VC

STM32L152CCT6, STM32L152CCU6

STM32L152RCT6

STM32L152UCY6

STM32L152VCT6, STM32L152VCH6

LQFP100 (14 × 14 mm)

LQFP64 (10 × 10 mm)

LQFP48 (7 x 7 mm)

UFBGA100

(7 x 7 mm)

WLCSP63

(0,400 mm

pitch)

UFQFPN48

(7x7 mm)

1
2
3
...
»

Summary of Contents for STM32L151CCT6

Page 1: ... I Os 70 I Os 5V tolerant all mappable on 16 external interrupt vectors Memories 256 KB Flash memory with ECC 32 KB RAM 8 KB of true EEPROM with ECC 128 Byte backup register LCD Driver except STM32L151xC devices up to 8x40 segments contrast adjustment blinking mode step up converter Rich analog peripherals down to 1 8 V 2x operational amplifiers 12 bit ADC 1Msps up to 25 channels 12 bit DAC 2 chan...

Page 2: ...9 3 3 2 Power supply supervisor 19 3 3 3 Voltage regulator 20 3 3 4 Boot modes 20 3 4 Clock management 21 3 5 Low power real time clock and backup registers 23 3 6 GPIOs general purpose inputs outputs 23 3 7 Memories 24 3 8 DMA direct memory access 24 3 9 LCD liquid crystal display 25 3 10 ADC analog to digital converter 25 3 10 1 Temperature sensor 26 3 10 2 Internal voltage reference VREFINT 26 ...

Page 3: ...B 31 3 18 CRC cyclic redundancy check calculation unit 31 3 19 Development support 32 3 19 1 Serial wire JTAG debug port SWJ DP 32 3 19 2 Embedded Trace Macrocell 32 4 Pin descriptions 33 5 Memory mapping 52 6 Electrical characteristics 53 6 1 Parameter conditions 53 6 1 1 Minimum and maximum values 53 6 1 2 Typical values 53 6 1 3 Typical curves 53 6 1 4 Loading capacitor 53 6 1 5 Pin input volta...

Page 4: ... 18 DAC electrical specifications 104 6 3 19 Operational amplifier characteristics 106 6 3 20 Temperature sensor characteristics 108 6 3 21 Comparator 108 6 3 22 LCD controller 110 7 Package characteristics 111 7 1 Package information 111 7 1 1 LQFP100 14 x 14 mm 100 pin low profile quad flat package information 111 7 1 2 LQFP64 10 x 10 mm 64 pin low profile quad flat package information 114 7 1 3...

Page 5: ...ode code with data processing running from RAM 63 Table 20 Current consumption in Sleep mode 64 Table 21 Current consumption in Low power run mode 65 Table 22 Current consumption in Low power sleep mode 66 Table 23 Typical and maximum current consumptions in Stop mode 67 Table 24 Typical and maximum current consumptions in Standby mode 69 Table 25 Peripheral current consumption 70 Table 26 Low pow...

Page 6: ...62 Temperature sensor characteristics 108 Table 63 Comparator 1 characteristics 108 Table 64 Comparator 2 characteristics 109 Table 65 LCD controller characteristics 110 Table 66 LQPF100 14 x 14 mm 100 pin low profile quad flat package mechanical data 112 Table 67 LQFP64 10 x 10 mm 64 pin low profile quad flat package mechanical data 115 Table 68 LQFP48 7 x 7 mm 48 pin low profile quad flat packag...

Page 7: ...24 SPI timing diagram master mode 1 95 Figure 25 USB timings definition of data signal rise and fall time 96 Figure 26 I2 S slave timing diagram Philips protocol 1 98 Figure 27 I2 S master timing diagram Philips protocol 1 98 Figure 28 ADC accuracy characteristics 102 Figure 29 Typical connection diagram using the ADC 102 Figure 30 Maximum dynamic current consumption on VREF supply pin during ADC ...

Page 8: ...List of figures STM32L151xC STM32L152xC 8 135 DocID022799 Rev 10 Figure 47 WLCSP63 device marking example 127 Figure 48 Thermal resistance suffix 6 129 Figure 49 Thermal resistance suffix 7 129 ...

Page 9: ... the ultra low power STM32L151xC and STM32L152xC microcontroller family suitable for a wide range of applications Medical and handheld equipment Application control and user interface PC peripherals gaming GPS and sport equipment Alarm systems wired and wireless sensors video intercom Utility metering This STM32L151xC and STM32L152xC datasheet should be read in conjunction with the STM32L1xxxx ref...

Page 10: ...er the STM32L151xC and STM32L152xC devices contain standard and advanced communication interfaces up to two I2Cs three SPIs two I2S three USARTs and an USB The STM32L151xC and STM32L152xC devices offer up to 23 capacitive sensing channels to simply add a touch sensing functionality to any application They also include a real time clock and a set of backup registers that remain powered in Standby m...

Page 11: ...ART 3 USB 1 GPIOs 37 51 83 Operation amplifiers 2 12 bit synchronized ADC Number of channels 1 14 1 21 1 25 12 bit DAC Number of channels 2 2 LCD 1 COM x SEG 1 STM32L152xx devices only 1 4x18 1 4x32 or 8x28 1 4x44 or 8x40 Comparators 2 Capacitive sensing channels 16 23 Max CPU frequency 32 MHz Operating voltage 1 8 V to 3 6 V down to 1 65 V at power down with BOR option 1 65 V to 3 6 V without BOR...

Page 12: ...ate highly energy efficient cores with both Harvard architecture and pipelined execution advanced STM8 core for STM8L families and ARM Cortex M3 core for STM32L family In addition specific care for the design architecture has been taken to optimize the mA DMIPS and mA MHz ratios This allows the ultra low power performance to range from 5 up to 33 3 DMIPs 2 2 2 Shared peripherals STM8L15xxx STM32L1...

Page 13: ... 2 3257 5 6 7 0 56 ELWV ELW 63 6 75 75 75 75 75 6 VWHP DS VHQV 6XSSO PRQLWRULQJ 9 9 9 9 6XSSO PRQLWRULQJ DS VHQVLQJ 3 2 3257 3 2 3257 3 PD 0 3 PD 0 3 ORFN 0JPW 9 13 9 10 9287 9 13 9 10 9287 57 B287 3 3 7 6 706 6 7 7 2 DV 352 5 0 7 227 9 9 25 9UHI 0 38 3 0 FKDQQHOV 3 0 FKDQQHOV 3 3 3 9 9 9 WR 9 9VV 26 B 1 26 B287 7 03 5 FKDQQHOV FKDQQHOV FKDQQHOV FKDQQHOV 5 7 76 576 6PDUW DUG DV 5 7 76 576 6PDUW DU...

Page 14: ... oscillator set to the minimum clock 131 kHz execution from SRAM or Flash memory and internal regulator in low power mode to minimize the regulator s operating current In low power run mode the clock frequency and the number of enabled peripherals are both limited Low power sleep mode This mode is achieved by entering Sleep mode with the internal voltage regulator in Low power mode to minimize the...

Page 15: ...ing edge on one of the three WKUP pins RTC alarm Alarm A or Alarm B RTC tamper event RTC timestamp event or RTC Wakeup event occurs Standby mode without RTC Standby mode is used to achieve the lowest power consumption The internal voltage regulator is switched off so that the entire VCORE domain is powered off The PLL MSI RC HSI and LSI RC HSE and LSE crystal oscillators are also switched off Afte...

Page 16: ...For example to switch from 4 2 MHz to 32 MHz you can switch from 4 2 MHz to 16 MHz wait 5 µs then switch from 16 MHz to 32 MHz 2 Should be USB compliant from I O voltage standpoint the minimum VDD is 3 0 V Table 3 Functionalities depending on the operating power supply range continued Functionalities depending on the operating power supply range Operating power supply range DAC and ADC operation U...

Page 17: ... Y Y Y Y EEPROM Y Y Y Y Y Brown out rest BOR Y Y Y Y Y Y Y DMA Y Y Y Y Programmable Voltage Detector PVD Y Y Y Y Y Y Y Power On Reset POR Y Y Y Y Y Y Y Power Down Rest PDR Y Y Y Y Y Y High Speed Internal HSI Y Y High Speed External HSE Y Y Low Speed Internal LSI Y Y Y Y Y Low Speed External LSE Y Y Y Y Y Multi Speed Internal MSI Y Y Y Y Inter Connect Controller Y Y Y Y RTC Y Y Y Y Y Y Y RTC Tamper...

Page 18: ...P amp Y Y Y Y Y Comparators Y Y Y Y Y Y 16 bit and 32 bit Timers Y Y Y Y IWDG Y Y Y Y Y Y Y Y WWDG Y Y Y Y Touch sensing Y Y Systic Timer Y Y Y Y GPIOs Y Y Y Y Y Y 3 pins Wakeup time to Run mode 0 µs 0 4 µs 3 µs 46 µs 8 µs 58 µs Consumption VDD 1 8 to 3 6 V Typ Down to 185 µA MHz from Flash Down to 34 5 µA MHz from Flash Down to 8 6 µA Down to 4 4 µA 0 43 µA no RTC VDD 1 8V 0 29 µA no RTC VDD 1 8V...

Page 19: ...e block provides flexible interrupt management features with minimal interrupt latency 3 3 Reset and supply management 3 3 1 Power supply schemes VDD 1 65 to 3 6 V external power supply for I Os and the internal regulator Provided externally through VDD pins VSSA VDDA 1 65 to 3 6 V external analog power supplies for ADC reset blocks RCs and PLL minimum voltage to be applied to VDDA is 1 8 V when t...

Page 20: ...sen by software with a step around 200 mV An interrupt can be generated when VDD VDDA drops below the VPVD threshold and or when VDD VDDA is higher than the VPVD threshold The interrupt service routine can then generate a warning message and or put the MCU into a safe state The PVD is enabled by software 3 3 3 Voltage regulator The regulator has three operation modes main MR low power LPR and powe...

Page 21: ...he MSI frequency can be trimmed by software down to a 0 5 accuracy Auxiliary clock source two ultra low power clock sources that can be used to drive the LCD controller and the real time clock 32 768 kHz low speed external crystal LSE 37 kHz low speed internal RC LSI also used to drive the independent watchdog The LSI clock can be measured using the high speed internal RC oscillator for greater pr...

Page 22: ...OL LOCK 7ATCHDOG ENABLE 24 ENABLE CK HSI CK HSE 3 PRESENT OR NOT 3 TEMPO CK PLL PRESCALER 0 0 CK USB 6CO 6CO MUST BE AT Z 4 393 05 072 53 4 4 0 0 USBEN AND NOT DEEPSLEEP TIMER EN AND NOT DEEPSLEEP APB PERIPHEN AND NOT DEEPSLEEP APB PERIPHEN AND NOT DEEPSLEEP NOT SLEEP OR DEEPSLEEP NOT SLEEP OR DEEPSLEEP NOT DEEPSLEEP NOT DEEPSLEEP 3TANDBY SUPPLIED VOLTAGE DOMAIN 3YSTEM CLOCK IF 0 PRESC X ELSE X CK...

Page 23: ...ese pins can reset backup register and generate an interrupt To prevent false tamper event like ESD event these three tamper inputs can be digitally filtered 3 6 GPIOs general purpose inputs outputs Each of the GPIO pins can be configured by software as output push pull or open drain as input with or without pull up or pull down or as peripheral alternate function Most of the GPIO pins are shared ...

Page 24: ... either debug features are connected or boot in RAM is selected Level 2 chip readout protection debug features ARM Cortex M3 JTAG and serial wire and boot in RAM selection disabled JTAG fuse The whole non volatile memory embeds the error correction code ECC feature The user area of the Flash memory can be protected against Dbus read access by PCROP feature see RM0038 for details 3 8 DMA direct mem...

Page 25: ...e shot or scan mode In scan mode automatic conversion is performed on a selected group of analog inputs with up to 24 external channels in a group The ADC can be served by the DMA controller An analog watchdog feature allows very precise monitoring of the converted voltage of one some or all scanned channels An interrupt is generated when the converted voltage is outside the programmed thresholds ...

Page 26: ...e changes only To improve the accuracy of the temperature sensor measurement each device is individually factory calibrated by ST The temperature sensor factory calibration data are stored by ST in the system memory area accessible in read only mode See Table 61 Temperature sensor calibration values 3 10 2 Internal voltage reference VREFINT The internal voltage reference VREFINT provides a stable ...

Page 27: ...2L151xC and STM32L152xC devices The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels 3 12 Operational amplifier The STM32L151xC and STM32L152xC devices embed two operational amplifiers with external or internal follower routing capability or even amplifier and filter capability with external components When one operational amplifier is s...

Page 28: ...oftware and timer capacitive sensing acquisition modes are supported Capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric glass plastic The capacitive variation introduced by the finger or any conductive object is measured using a proven implementation based on a surface charge transfer acquisition principle It ...

Page 29: ...n These timers are capable of handling quadrature incremental encoder signals and the digital outputs from 1 to 3 hall effect sensors TIM10 TIM11 and TIM9 TIM10 and TIM11 are based on a 16 bit auto reload upcounter TIM9 is based on a 16 bit auto reload up down counter They include a 16 bit prescaler TIM10 and TIM11 feature one independent channel whereas TIM9 has two independent channels for input...

Page 30: ...ee running It can be used as a watchdog to reset the device when a problem occurs It is clocked from the main clock It has an early warning interrupt capability and the counter can be frozen in debug mode 3 17 Communication interfaces 3 17 1 I C bus Up to two I C bus interfaces can operate in multimaster and slave modes They can support standard and fast modes They support dual slave addressing 7 ...

Page 31: ...mbed a USB device peripheral compatible with the USB full speed 12 Mbit s The USB interface implements a full speed 12 Mbit s function interface It has software configurable endpoint setting and supports suspend resume The dedicated 48 MHz clock is generated from the internal main PLL the clock source must use a HSE crystal oscillator 3 18 CRC cyclic redundancy check calculation unit The CRC cycli...

Page 32: ...d with a JTAG fuse 3 19 2 Embedded Trace Macrocell The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32L151xC and STM32L152xC device through a small number of ETM pins to an external hardware trace port analyzer TPA device The TPA is connected to a host computer using USB ...

Page 33: ...out 1 This figure shows the package top view AI F 0 3 26 B 1 3 26 B287 3 3 83 3 26 B287 3 966 95 95 9 3 3 3 3 8 3 9 966B 9 B 1567 3 3 3 83 3 3 3 3 966B 966B 9 B 3 3 3 3 227 3 9 B 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 966B 9 B 3 3 3 3 3 3 3 3 3 3 966B 9 B 3 3 26 B 1 ...

Page 34: ...nout 1 This figure shows the package top view 6 633 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 633 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 633 6 6 633 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 50 6 0 7 50 0 3 0 3 54 633 6 0 3 0 3 54 234 0 0 0 0 633 62 62 6 0 7 50 0 0 AI C 1 0 0 0 ...

Page 35: ...riptions 52 Figure 5 STM32L15xRC LQFP64 pinout 1 This figure shows the package top view 6 0 7 50 0 3 0 3 54 0 3 0 3 54 234 0 0 0 0 633 6 0 7 50 0 0 6 633 0 0 4 0 0 0 0 0 0 0 0 0 0 0 6 633 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 633 6 0 0 0 0 0 0 0 0 0 0 0 633 6 1 0 AI C ...

Page 36: ...6 135 DocID022799 Rev 10 Figure 6 STM32L15xUC WLCSP63 ballout 1 This figure shows the package top view 3 6 633 0 0 0 6 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 633 4 0 633 6 0 0 0 0 234 6 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 633 633 0 0 0 0 0 0 ...

Page 37: ...152xC Pin descriptions 52 Figure 7 STM32L15xCC UFQFPN48 pinout 1 This figure shows the package top view 6 33 4 0 0 0 0 0 0 0 6 633 0 5 1 0 0 633 0 6 0 0 7 50 0 0 0 0 6 0 0 0 0 0 0 0 0 6 33 AI D 0 0 0 0 0 0 6 0 7 50 0 3 0 3 54 0 3 0 3 54 234 0 0 6 ...

Page 38: ... and after reset is the same as the actual pin name Pin type S Supply pin I Input only pin I O Input output pin I O structure FT 5 V tolerant I O TC Standard 3 3 V I O B Dedicated BOOT0 pin RST Bidirectional reset pin with embedded weak pull up resistor Notes Unless otherwise specified by a note all I Os are set as floating inputs during and after reset 9 B 966B 3 3 3 3 3 3 3 4 3 06 9 3 83 3 26 B ...

Page 39: ...unction 2 after reset Pin functions UFBGA100 LQFP100 LQFP64 WLCSP63 LQFP48 or UFQFPN48 Alternate functions Additional functions B2 1 PE2 I O FT PE2 TIM3_ETR LCD_SEG38 TRACECLK A1 2 PE3 I O FT PE3 TIM3_CH1 LCD_SEG39 TRACED0 B1 3 PE4 I O FT PE4 TIM3_CH2 TRACED1 C2 4 PE5 I O FT PE5 TIM9_CH1 TRACED2 D2 5 PE6 WKUP3 I O FT PE6 TIM9_CH2 TRACED3 WKUP3 RTC_TAMP3 E2 6 1 C7 1 VLCD 3 S VLCD C1 7 2 D5 2 PC13 W...

Page 40: ...WKUP1 I O FT PA0 TIM2_CH1_ETR TIM5_CH1 USART2_CTS WKUP1 RTC_TAMP2 ADC_IN0 COMP1_INP M2 24 15 G5 11 PA1 I O FT PA1 TIM2_CH2 TIM5_CH2 USART2_RTS LCD_SEG0 ADC_IN1 COMP1_INP OPAMP1_VINP K3 25 16 H6 12 PA2 I O FT PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 USART2_TX LCD_SEG1 ADC_IN2 COMP1_INP OPAMP1_VINM L3 26 17 J7 13 PA3 I O TC PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 USART2_RX LCD_SEG2 ADC_IN3 COMP1_INP OPAMP1_VOUT E3 27 ...

Page 41: ...14 COMP1_INP L5 34 25 J4 PC5 I O FT PC5 LCD_SEG23 ADC_IN15 COMP1_INP M5 35 26 J3 18 PB0 I O TC PB0 TIM3_CH3 LCD_SEG5 ADC_IN8 COMP1_INP OPAMP2_VOUT VLCDRAIL3 VREF_OUT M6 36 27 H3 19 PB1 I O FT PB1 TIM3_CH4 LCD_SEG6 ADC_IN9 COMP1_INP VREF_OUT L6 37 28 G3 20 PB2 I O FT PB2 BOOT1 BOOT1 COMP1_INP VLCDRAIL1 ADCIN0b M7 38 PE7 I O TC PE7 ADC_IN22 COMP1_INP L7 39 PE8 I O TC PE8 ADC_IN23 COMP1_INP M8 40 PE9...

Page 42: ...S_1 S VSS_1 G12 50 32 H1 24 VDD_1 S VDD_1 L12 51 33 G2 25 PB12 I O FT PB12 TIM10_CH1 I2C2_SMBA SPI2_NSS I2S2_WS USART3_CK LCD_SEG12 ADC_IN18 COMP1_INP VLCDRAIL2 K12 52 34 G1 26 PB13 I O FT PB13 TIM9_CH1 SPI2_SCK I2S2_CK USART3_CTS LCD_SEG13 ADC_IN19 COMP1_INP K11 53 35 F3 27 PB14 I O FT PB14 TIM9_CH2 SPI2_MISO USART3_RTS LCD_SEG14 ADC_IN20 COMP1_INP K10 54 36 F2 28 PB15 I O FT PB15 TIM11_CH1 SPI2_...

Page 43: ...LCD_SEG24 E11 64 38 E1 PC7 I O FT PC7 TIM3_CH2 I2S3_MCK LCD_SEG25 E10 65 39 D1 PC8 I O FT PC8 TIM3_CH3 LCD_SEG26 D12 66 40 E2 PC9 I O FT PC9 TIM3_CH4 LCD_SEG27 D11 67 41 E3 29 PA8 I O FT PA8 USART1_CK MCO LCD_COM0 D10 68 42 C1 30 PA9 I O FT PA9 USART1_TX LCD_COM1 C12 69 43 D2 31 PA10 I O FT PA10 USART1_RX LCD_COM2 B12 70 44 B1 32 PA11 I O FT PA11 USART1_CTS SPI1_MISO USB_DM A12 71 45 D3 33 PA12 I ...

Page 44: ...RT3_TX LCD_SEG28 LCD_SEG40 LCD_COM4 C10 79 52 A3 PC11 I O FT PC11 SPI3_MISO USART3_RX LCD_SEG29 LCD_SEG41 LCD_COM5 B10 80 53 B4 PC12 I O FT PC12 SPI3_MOSI I2S3_SD USART3_CK LCD_SEG30 LCD_SEG42 LCD_COM6 C9 81 PD0 I O FT PD0 TIM9_CH1 SPI2_NSS I2S2_WS B9 82 PD1 I O FT PD1 SPI2_SCK I2S2_CK C8 83 54 A4 PD2 I O FT PD2 TIM3_ETR LCD_SEG31 LCD_SEG43 LCD_COM7 Table 9 STM32L151xC and STM32L152xC pin definiti...

Page 45: ..._SMBA SPI1_MOSI SPI3_MOSI I2S3_SD LCD_SEG9 COMP2_INP B5 92 58 B5 42 PB6 I O FT PB6 TIM4_CH1 I2C1_SCL USART1_TX COMP2_INP B4 93 59 C5 43 PB7 I O FT PB7 TIM4_CH2 I2C1_SDA USART1_RX COMP2_INP PVD_IN A4 94 60 A6 44 BOOT0 I B BOOT0 A3 95 61 B6 45 PB8 I O FT PB8 TIM4_CH3 TIM10_CH1 I2C1_SCL LCD_SEG16 B3 96 62 C6 46 PB9 I O FT PB9 TIM4_CH4 TIM11_CH1 I2C1_SDA LCD_COM3 C3 97 PE0 I O FT PE0 TIM4_ETR TIM10_CH...

Page 46: ...illator is off The LSE has priority over the GPIO function For more details refer to Using the OSC32_IN OSC32_OUT pins as GPIO PC14 PC15 port pins section in the STM32L151xx STM32L152xx and STM32L162xx reference manual RM0038 5 The PH0 and PH1 I Os are only configured as OSC_IN OSC_OUT when the HSE oscillator is ON by setting the HSEON bit in the RCC_CR register The HSE oscillator pins OSC_IN OSC_...

Page 47: ...IM2_CH3 TIM5_CH3 TIM9_CH1 USART2_TX SEG1 TIMx_IC3 EVENT OUT PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 USART2_RX SEG2 TIMx_IC4 EVENT OUT PA4 SPI1_NSS SPI3_NSS I2S3_WS USART2_CK TIMx_IC1 EVENT OUT PA5 TIM2_CH1_ETR SPI1_SCK TIMx_IC2 EVENT OUT PA6 TIM3_CH1 TIM10_ CH1 SPI1_MISO SEG3 TIMx_IC3 EVENT OUT PA7 TIM3_CH2 TIM11_ CH1 SPI1_MOSI SEG4 TIMx_IC4 EVENT OUT PA8 MCO USART1_CK COM0 TIMx_IC1 EVENT OUT PA9 USART1_TX...

Page 48: ...T PB10 TIM2_CH3 I2C2_SCL USART3_TX SEG10 EVENT OUT PB11 TIM2_CH4 I2C2_SDA USART3_RX SEG11 EVENT OUT PB12 TIM10_CH1 I2C2_SMBA SPI2_NSS I2S2_WS USART3_CK SEG12 EVENT OUT PB13 TIM9_CH1 SPI2_SCK I2S2_CK USART3_CTS SEG13 EVENT OUT PB14 TIM9_CH2 SPI2_MISO USART3_RTS SEG14 EVENT OUT PB15 TIM11_CH1 SPI2_MOSI I2S2_SD SEG15 EVENT OUT PC0 SEG18 TIMx_IC1 EVENT OUT PC1 SEG19 TIMx_IC2 EVENT OUT PC2 SEG20 TIMx_I...

Page 49: ...EG29 SEG41 TIMx_IC4 EVENT OUT PC12 SPI3_MOSI I2S3_SD USART3_CK COM6 SEG30 SEG42 TIMx_IC1 EVENT OUT PC13 WKUP2 TIMx_IC2 EVENT OUT PC14 OSC32_IN TIMx_IC3 EVENT OUT PC15 OSC32_ OUT TIMx_IC4 EVENT OUT PD0 TIM9_CH1 SPI2_NSS I2S2_WS TIMx_IC1 EVENT OUT PD1 SPI2 SCK I2S2_CK TIMx_IC2 EVENT OUT PD2 TIM3_ETR COM7 SEG31 SEG43 TIMx_IC3 EVENT OUT Table 10 Alternate function input output continued Port name Digi...

Page 50: ... SEG33 TIMx_IC2 EVENT OUT PD14 TIM4_CH3 SEG34 TIMx_IC3 EVENT OUT PD15 TIM4_CH4 SEG35 TIMx_IC4 EVENT OUT PE0 TIM4_ETR TIM10_CH1 SEG36 TIMx_IC1 EVENT OUT PE1 TIM11_CH1 SEG37 TIMx_IC2 EVENT OUT PE2 TRACECK TIM3_ETR SEG 38 TIMx_IC3 EVENT OUT PE3 TRACED0 TIM3_CH1 SEG 39 TIMx_IC4 EVENT OUT PE4 TRACED1 TIM3_CH2 TIMx_IC1 EVENT OUT PE5 TRACED2 TIM9_CH1 TIMx_IC2 EVENT OUT PE6 WKUP3 TRACED3 TIM9_CH2 TIMx_IC3...

Page 51: ...SPI1_NSS TIMx_IC1 EVENT OUT PE13 SPI1_SCK TIMx_IC2 EVENT OUT PE14 SPI1_MISO TIMx_IC3 EVENT OUT PE15 SPI1_MOSI TIMx_IC4 EVENT OUT PH0OSC _IN PH1OSC_ OUT PH2 Table 10 Alternate function input output continued Port name Digital alternate function number AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO11 AFIO14 AFIO15 Alternate function SYSTEM TIM2 TIM3 4 5 TIM9 10 11 I2C1 2 SPI1 2 SPI3 USART1 2 3...

Page 52: ...HERALS 32 O RTEX NTERNAL 0ERIPHERALS 3 6 BYTE 53 4 4 4 X X X X X 0ORT 0ORT 0ORT 0ORT 0ORT 0ORT X X X X X X 0 2 LASH MEMORY 3YSTEM MEMORY LIASED TO LASH OR SYSTEM MEMORY DEPENDING ON 4 PINS ATA 02 RESERVED RESERVED RESERVED RESERVED RESERVED ON VOLATILE MEMORY RESERVED PTION BYTE RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X ...

Page 53: ...sample tests and represent the mean value plus or minus three times the standard deviation mean 3σ 6 1 2 Typical values Unless otherwise specified typical data are based on TA 25 C VDD 3 6 V for the 1 65 V VDD 3 6 V voltage range They are given only as design guidelines and are not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion...

Page 54: ...v 10 6 1 6 Power supply scheme Figure 12 Power supply scheme 06 9 QDORJ 26 3 203 9 3 2V 287 1 HUQHO ORJLF 38 LJLWDO 0HPRULHV 6WDQGE SRZHU FLUFXLWU 6 57 DNH XS ORJLF 57 EDFNXS UHJLVWHUV 1 î Q î 5HJXODWRU 966 9 95 95 966 HYHO VKLIWHU 2 RJLF 9 Q 95 Q 9 1 QXPEHU RI 9 966 SDLUV ...

Page 55: ...source VSEL switch is open 2 Option 2 LCD power supply is provided by the internal step up converter VSEL switch is closed an external capacitance is needed for correct behavior of this converter 6 1 8 Current consumption measurement Figure 14 Current consumption measurement scheme 06 9 9 1 1 Q 6WHS XS RQYHUWHU 966 1 9 Q 9 9 UDLO 9 UDLO 9 UDLO 9 3 RU 3 3 3 RU 3 7 UDLO 96 UDLO UDLO 2SWLRQ 2SWLRQ 1 ...

Page 56: ... values Table 12 Current characteristics Symbol Ratings Max Unit IVDD Σ Total current into sum of all VDD_x power lines source 1 100 mA IVSS Σ 2 Total current out of sum of all VSS_x ground lines sink 1 100 IVDD PIN Maximum current into each VDD_x power pin source 1 70 IVSS PIN Maximum current out of each VSS_x ground pin sink 1 70 IIO Output current sunk by any I O and control pin 25 Output curre...

Page 57: ...er Conditions Min Max Unit fHCLK Internal AHB clock frequency 0 32 MHz fPCLK1 Internal APB1 clock frequency 0 32 fPCLK2 Internal APB2 clock frequency 0 32 VDD Standard operating voltage BOR detector disabled 1 65 3 6 V BOR detector enabled at power on 1 8 3 6 BOR detector disabled after power on 1 65 3 6 VDDA 1 Analog operating voltage ADC and DAC not used Must be the same voltage as VDD 2 1 65 3 ...

Page 58: ...cs on page 128 5 In low power dissipation state TA can be extended to 40 C to 105 C temperature range as long as TJ does not exceed TJ max see Table 72 Thermal characteristics on page 128 Table 14 General operating conditions continued Symbol Parameter Conditions Min Max Unit Table 15 Embedded reset and power control block characteristics Symbol Parameter Conditions Min Typ Max Unit tVDD 1 VDD ris...

Page 59: ... 2 38 VPVD3 PVD threshold 3 Falling edge 2 39 2 44 2 48 Rising edge 2 47 2 54 2 58 VPVD4 PVD threshold 4 Falling edge 2 57 2 64 2 69 Rising edge 2 68 2 74 2 79 VPVD5 PVD threshold 5 Falling edge 2 77 2 83 2 88 Rising edge 2 87 2 94 2 99 VPVD6 PVD threshold 6 Falling edge 2 97 3 05 3 09 Rising edge 3 08 3 15 3 20 Vhyst Hysteresis voltage BOR0 threshold 40 mV All BOR and PVD thresholds excepting BOR...

Page 60: ... uncertainties due to ADC and VDDA VREF values 5 mV TCoeff 3 Temperature coefficient 40 C TJ 110 C 20 50 ppm C 0 C TJ 50 C 20 ACoeff 3 Long term stability 1000 hours T 25 C 1000 ppm VDDCoeff 3 Voltage coefficient 3 0 V VDDA 3 6 V 2000 ppm V TS_vrefint 3 ADC sampling time when reading the internal reference voltage 4 µs TADC_BUF 3 4 Startup time of reference voltage buffer for ADC 10 µs IBUF_ADC 3 ...

Page 61: ... C and VDD supply voltage conditions summarized in Table 14 General operating conditions unless otherwise specified The MCU is placed under the following conditions All I O pins are configured in analog input mode All peripherals are disabled except when explicitly mentioned The Flash memory access time 64 bit access and prefetch is adjusted depending on fHCLK frequency and voltage range to provid...

Page 62: ...z 215 400 µA 2 MHz 400 600 4 MHz 725 960 Range 2 VCORE 1 5 V VOS 1 0 10 4 MHz 0 915 1 1 mA 8 MHz 1 75 2 1 16 MHz 3 4 3 9 Range 1 VCORE 1 8 V VOS 1 0 01 8 MHz 2 1 2 8 16 MHz 4 2 4 9 32 MHz 8 25 9 4 HSI clock source 16 MHz Range 2 VCORE 1 5 V VOS 1 0 10 16 MHz 3 5 4 Range 1 VCORE 1 8 V VOS 1 0 01 32 MHz 8 2 9 6 MSI clock 65 kHz Range 3 VCORE 1 2 V VOS 1 0 11 65 kHz 40 5 110 µA MSI clock 524 kHz 524 ...

Page 63: ...µA 2 MHz 345 410 4 MHz 645 880 3 Range 2 VCORE 1 5 V VOS 1 0 10 4 MHz 0 755 1 4 mA 8 MHz 1 5 2 1 16 MHz 3 3 5 Range 1 VCORE 1 8 V VOS 1 0 01 8 MHz 1 8 2 8 16 MHz 3 6 4 1 32 MHz 7 15 8 3 HSI clock source 16 MHz Range 2 VCORE 1 5 V VOS 1 0 10 16 MHz 2 95 3 5 Range 1 VCORE 1 8 V VOS 1 0 01 32 MHz 7 15 8 4 MSI clock 65 kHz Range 3 VCORE 1 2 V VOS 1 0 11 65 kHz 38 5 85 µA MSI clock 524 kHz 524 kHz 110 ...

Page 64: ...CORE 1 2 V VOS 1 0 11 65 kHz 19 60 MSI clock 524 kHz 524 kHz 33 99 MSI clock 4 2 MHz 4 2 MHz 145 210 Supply current in Sleep mode Flash ON fHSE fHCLK up to 16 MHz included fHSE fHCLK 2 above 16 MHz PLL ON 2 Range 3 VCORE 1 2 V VOS 1 0 11 1 MHz 60 5 130 2 MHz 89 5 190 4 MHz 150 320 Range 2 VCORE 1 5 V VOS 1 0 10 4 MHz 180 320 8 MHz 320 460 16 MHz 605 840 Range 1 VCORE 1 8 V VOS 1 0 01 8 MHz 380 540...

Page 65: ... 14 16 TA 85 C 24 29 TA 105 C 40 51 MSI clock 131 kHz fHCLK 131 kHz TA 40 C to 25 C 26 29 TA 55 C 28 31 TA 85 C 36 42 TA 105 C 52 64 All peripherals OFF code executed from Flash VDD from 1 65 V to 3 6 V MSI clock 65 kHz fHCLK 32 kHz TA 40 C to 25 C 20 24 TA 85 C 32 37 TA 105 C 49 61 MSI clock 65 kHz fHCLK 65 kHz TA 40 C to 25 C 26 30 TA 85 C 38 44 TA 105 C 55 67 MSI clock 131 kHz fHCLK 131 kHz TA ...

Page 66: ... ON TA 40 C to 25 C 15 17 TA 85 C 20 23 TA 105 C 28 33 MSI clock 131 kHz fHCLK 131 kHz Flash ON TA 40 C to 25 C 17 19 TA 55 C 18 21 TA 85 C 22 25 TA 105 C 30 35 TIM9 and USART1 enabled Flash ON VDD from 1 65 V to 3 6 V MSI clock 65 kHz fHCLK 32 kHz TA 40 C to 25 C 14 16 TA 85 C 19 22 TA 105 C 27 32 MSI clock 65 kHz fHCLK 65 kHz TA 40 C to 25 C 15 17 TA 85 C 20 23 TA 105 C 28 33 MSI clock 131 kHz f...

Page 67: ...TA 85 C 3 4 10 TA 105 C 6 35 23 LCD ON static duty 2 TA 40 C to 25 C 1 55 6 TA 55 C 2 15 7 TA 85 C 3 55 12 TA 105 C 6 3 27 LCD ON 1 8 duty 3 TA 40 C to 25 C 3 9 10 TA 55 C 4 65 11 TA 85 C 6 25 16 TA 105 C 9 1 44 RTC clocked by LSE external quartz 32 768kHz regulator in LP mode HSI and HSE OFF no independent watchdog 4 LCD OFF TA 40 C to 25 C 1 5 TA 55 C 2 15 TA 85 C 3 7 TA 105 C 6 75 LCD ON static...

Page 68: ...results not tested in production unless otherwise specified 2 LCD enabled with external VLCD static duty division ratio 256 all pixels active no LCD connected 3 LCD enabled with external VLCD 1 8 duty 1 3 bias division ratio 64 all pixels active no LCD connected 4 Based on characterization done with a 32 768 kHz crystal MC306 G 06Q 32 768 manufacturer JFVNY with two 6 8 pF loading capacitors 5 Gua...

Page 69: ...nabled RTC clocked by LSI no independent watchdog TA 40 C to 25 C VDD 1 8 V 0 905 µA TA 40 C to 25 C 1 15 1 9 TA 55 C 1 5 2 2 TA 85 C 1 75 4 TA 105 C 2 1 8 3 2 RTC clocked by LSE external quartz no independent watchdog 3 TA 40 C to 25 C VDD 1 8 V 0 98 TA 40 C to 25 C 1 3 TA 55 C 1 7 TA 85 C 2 05 TA 105 C 2 45 IDD Standby Supply current in Standby mode RTC disabled Independent watchdog and LSI enab...

Page 70: ...E 1 2 V VOS 1 0 11 Low power sleep and run APB1 TIM2 11 2 8 9 7 0 8 9 µA MHz fHCLK TIM3 11 2 9 0 7 1 9 0 TIM4 12 9 10 4 8 2 10 4 TIM5 14 4 11 5 9 0 11 5 TIM6 4 0 3 1 2 4 3 1 TIM7 3 8 3 0 2 3 3 0 LCD 5 8 4 6 3 6 4 6 WWDG 2 9 2 3 1 8 2 3 SPI2 6 5 5 2 4 1 5 2 SPI3 5 9 4 6 3 6 4 6 USART2 8 8 7 0 5 5 7 0 USART3 8 4 6 8 5 3 6 8 I2C1 7 3 5 8 4 6 5 8 I2C2 7 9 6 3 5 0 6 3 USB 13 3 10 6 8 3 10 6 PWR 2 8 2 2...

Page 71: ...1450 IDD DAC 5 340 IDD COMP1 0 16 IDD COMP2 Slow mode 2 Fast mode 5 IDD PVD BOR 6 2 6 IDD IWDG 0 25 1 Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock enabled in the following conditions fHCLK 32 MHz range 1 fHCLK 16 MHz range 2 fHCLK 4 MHz range 3 fHCLK 64kHz Low power run sleep fAPB1 fHCLK fAPB2 fHCLK default prescaler value for each peripheral ...

Page 72: ...t between DAC in reset configuration and continuous DAC conversion of VDD 2 DAC is in buffered mode output is left floating 6 Including supply current of internal reference voltage Table 26 Low power mode wakeup timings Symbol Parameter Conditions Typ Max 1 1 Guaranteed by characterization not tested in production unless otherwise specified Unit tWUSLEEP Wakeup from Sleep mode fHCLK 32 MHz 0 4 µs ...

Page 73: ...in Figure 15 Figure 15 High speed external clock source AC timing diagram Table 27 High speed external user clock characteristics 1 1 Guaranteed by design not tested in production Symbol Parameter Conditions Min Typ Max Unit fHSE_ext User external clock source frequency CSS is on or PLL is used 1 8 32 MHz CSS is off PLL not used 0 8 32 MHz VHSEH OSC_IN input pin high level voltage 0 7VDD VDD V VHS...

Page 74: ...ternal components specified in Table 29 In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time Refer to the crystal resonator manufacturer for more details on the resonator characteristics frequency package accuracy Table 28 Low speed external user clock characteris...

Page 75: ...or 200 kΩ C Recommended load capacitance versus equivalent serial resistance of the crystal RS 3 RS 30 Ω 20 pF IHSE HSE driving current VDD 3 3 V VIN VSS with 30 pF load 3 mA IDD HSE HSE oscillator power consumption C 20 pF fOSC 16 MHz 2 5 startup 0 7 stabilized mA C 10 pF fOSC 16 MHz 2 5 startup 0 46 stabilized gm Oscillator transconductance Startup 3 5 mA V tSU HSE 4 Startup time VDD is stabiliz...

Page 76: ...le 30 LSE oscillator characteristics fLSE 32 768 kHz 1 1 Guaranteed by characterization results not tested in production Symbol Parameter Conditions Min Typ Max Unit fLSE Low speed external oscillator frequency 32 768 kHz RF Feedback resistor 1 2 MΩ C 2 2 Refer to the note and caution paragraphs below the table and to the application note AN2867 Oscillator design guide for ST microcontrollers Reco...

Page 77: ...capacitance Typically it is between 2 pF and 7 pF Caution To avoid exceeding the maximum value of CL1 and CL2 15 pF it is strongly recommended to use a resonator with a load capacitance CL 7 pF Never use a resonator with a load capacitance of 12 5 pF Example if you choose a resonator with a load capacitance of CL 6 pF and Cstray 2 pF then CL1 CL2 8 pF Figure 18 Typical application with a 32 768 kH...

Page 78: ... 5 ACCHSI 2 2 Guaranteed by characterization results not tested in production Accuracy of the factory calibrated HSI oscillator VDDA 3 0 V TA 25 C 1 3 3 Guaranteed by test in production 1 3 VDDA 3 0 V TA 0 to 55 C 1 5 1 5 VDDA 3 0 V TA 10 to 70 C 2 2 VDDA 3 0 V TA 10 to 85 C 2 5 2 VDDA 3 0 V TA 10 to 105 C 4 2 VDDA 1 65 V to 3 6 V TA 40 to 105 C 4 3 tSU HSI 2 HSI oscillator startup time 3 7 6 µs I...

Page 79: ...SI range 5 2 1 MSI range 6 4 2 ACCMSI Frequency error after factory calibration 0 5 DTEMP MSI 1 MSI oscillator frequency drift 0 C TA 105 C 3 DVOLT MSI 1 MSI oscillator frequency drift 1 65 V VDD 3 6 V TA 25 C 2 5 V IDD MSI 2 MSI oscillator power consumption MSI range 0 0 75 µA MSI range 1 1 MSI range 2 1 5 MSI range 3 2 5 MSI range 4 4 5 MSI range 5 8 MSI range 6 15 tSU MSI MSI oscillator startup...

Page 80: ... 5 2 MSI range 6 Voltage range 1 and 2 2 MSI range 3 Voltage range 3 3 fOVER MSI MSI oscillator frequency overshoot Any range to range 5 4 MHz Any range to range 6 6 1 This is a deviation for an individual part once the initial frequency has been measured 2 Guaranteed by characterization results not tested in production Table 33 MSI oscillator characteristics continued Symbol Parameter Condition T...

Page 81: ...input clock 2 2 Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT 2 24 MHz PLL input clock duty cycle 45 55 fPLL_OUT PLL output clock 2 32 MHz tLOCK PLL lock time PLL input 16 MHz PLL VCO 96 MHz 115 160 µs Jitter Cycle to cycle jitter 600 ps IDDA PLL Current consumption on VDDA 220 450 µA IDD PLL Current consump...

Page 82: ...mum current peak during the whole programming erase operation 1 5 2 5 mA Table 37 Flash memory and data EEPROM endurance and retention Symbol Parameter Conditions Value Unit Min 1 1 Guaranteed by characterization results not tested in production Typ Max NCYC 2 Cycling erase write Program memory TA 40 C to 105 C 10 kcycles Cycling erase write EEPROM data memory 300 tRET 2 2 Characterization is done...

Page 83: ...blems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level re...

Page 84: ...static discharge ESD Electrostatic discharges a positive then a negative pulse separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts n 1 supply pins This test conforms to the JESD22 A114 C101 standard Table 39 EMI characteristics Symbol Parameter Conditions Monitored frequency band M...

Page 85: ...tion is executed on the device the device is stressed by injecting current into the I O pins programmed in floating input mode While current is injected into the I O pin one at a time the device is checked for functional failures The failure is indicated by an out of range parameter ADC error above a certain limit higher than 5 LSB TUE out of conventional limits of induced leakage current on adjac...

Page 86: ... hysteresis 2 TC and FT I O 10 VDD 3 BOOT0 0 01 Ilkg Input leakage current 4 VSS VIN VDD I Os with LCD 50 nA VSS VIN VDD I Os with analog switches 50 VSS VIN VDD I Os with analog switches and LCD 50 VSS VIN VDD I Os with USB 250 VSS VIN VDD TC and FT I Os 50 FT I O VDD VIN 5V 10 µA RPU Weak pull up equivalent resistor 5 1 VIN VSS 30 45 60 kΩ RPD Weak pull down equivalent resistor 5 VIN VDD 30 45 6...

Page 87: ...e derived from tests performed under the conditions summarized in Table 14 All I Os are CMOS and TTL compliant Table 44 Output voltage characteristics Symbol Parameter Conditions Min Max Unit VOL 1 2 1 The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 12 and the sum of IIO I O ports and control pins must not exceed IVSS 2 Guaranteed by test in pr...

Page 88: ...3 6 V 2 MHz CL 50 pF VDD 1 65 V to 2 7 V 1 tf IO out tr IO out Output rise and fall time CL 50 pF VDD 2 7 V to 3 6 V 125 ns CL 50 pF VDD 1 65 V to 2 7 V 250 10 Fmax IO out Maximum frequency 3 CL 50 pF VDD 2 7 V to 3 6 V 10 MHz CL 50 pF VDD 1 65 V to 2 7 V 2 tf IO out tr IO out Output rise and fall time CL 50 pF VDD 2 7 V to 3 6 V 25 ns CL 50 pF VDD 1 65 V to 2 7 V 125 11 Fmax IO out Maximum freque...

Page 89: ...F OUT Table 46 NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit VIL NRST 1 NRST input low level voltage 0 3 VDD V VIH NRST 1 NRST input high level voltage 0 39VDD 0 59 VOL NRST 1 NRST output low level voltage IOL 2 mA 2 7 V VDD 3 6 V 0 4 IOL 1 5 mA 1 65 V VDD 2 7 V Vhys NRST 1 NRST Schmitt trigger voltage hysteresis 10 VDD 2 mV RPU Weak pull up equivalent resistor 3 VIN VSS 30...

Page 90: ...on the input output ction characteristics output compare input capture external clock PWM output DL E 670 538 1567 9 LOWHU QWHUQDO UHVHW WHUQDO UHVHW FLUFXLW Table 47 TIMx 1 characteristics 1 TIMx is used as a general term to refer to the TIM2 TIM3 and TIM4 timers Symbol Parameter Conditions Min Max Unit tres TIM Timer resolution time 1 tTIMxCLK fTIMxCLK 32 MHz 31 25 ns fEXT Timer external clock f...

Page 91: ...z to achieve standard mode I C frequencies It must be at least 4 MHz to achieve fast mode I C frequencies It must be a multiple of 10 MHz to reach the 400 kHz maximum I C fast mode clock Unit Min Max Min Max tw SCLL SCL clock low time 4 7 1 3 µs tw SCLH SCL clock high time 4 0 0 6 tsu SDA SDA setup time 250 100 ns th SDA SDA data hold time 3450 3 900 3 3 The maximum Data hold time has only to be m...

Page 92: ...DD_I2C 3 3 V 1 2 1 RP External pull up resistance fSCL I2C speed 2 For speeds around 200 kHz the tolerance on the achieved speed is of 5 For other speed ranges the tolerance on the achieved speed is 2 These variations depend on the accuracy of the external components used to design the application fSCL kHz I2C_CCR value RP 4 7 kΩ 400 0x801B 300 0x8024 200 0x8035 100 0x00A0 50 0x0140 20 0x0320 Ăŝϭϳ...

Page 93: ... mode 30 70 tsu NSS NSS setup time Slave mode 4tHCLK ns th NSS NSS hold time Slave mode 2tHCLK tw SCKH 2 tw SCKL 2 SCK high and low time Master mode tSCK 2 5 tSCK 2 3 tsu MI 2 Data input setup time Master mode 5 tsu SI 2 Slave mode 6 th MI 2 Data input hold time Master mode 5 th SI 2 Slave mode 5 ta SO 4 Data output access time Slave mode 0 3tHCLK tv SO 2 Data output valid time Slave mode 33 tv MO...

Page 94: ...asurement points are done at CMOS levels 0 3VDD and 0 7VDD DL F ŶƉƵƚ W сϬ DK EWhd D K KhdW hd W сϬ D K hd D E dϲ Khd E Khd WK сϬ WK сϭ dϭ E E ŝŶƉƵƚ ƚ h E Ϳ ƚĐ Ϳ ƚŚ E Ϳ ƚĂ KͿ ƚǁ Ϳ ƚǁ Ϳ ƚǀ KͿ ƚŚ KͿ ƚƌ Ϳ ƚĨ Ϳ ƚĚŝƐ KͿ ƚƐƵ Ϳ ƚŚ Ϳ DL 6 QSXW 3 026 1387 0 62 287 387 3 06 2 87 06 1 7 287 6 1 6 287 32 32 7 1 W68 166 WF 6 WK 166 WD 62 WZ 6 WZ 6 WY 62 WK 62 WU 6 WI 6 WGLV 62 WVX 6 WK 6 166 LQSXW ...

Page 95: ...trical characteristics 110 Figure 24 SPI timing diagram master mode 1 1 Measurement points are done at CMOS levels 0 3VDD and 0 7VDD AI 6 3 UTPUT 0 3 54054 3 054 0 3 3 54 4 3 54 3 0 0 4 54 33 INPUT TC 3 TW 3 TW 3 TR 3 TF 3 TH IGH 3 UTPUT 0 0 0 0 TSU TV TH ...

Page 96: ...VDD USB operating voltage 3 0 3 6 V VDI 2 2 Guaranteed by characterization results not tested in production Differential input sensitivity I USB_DP USB_DM 0 2 V VCM 2 Differential common mode range Includes VDI range 0 8 2 5 VSE 2 Single ended receiver threshold 1 3 2 0 Output levels VOL 3 3 Guaranteed by test in production Static output level low RL of 1 5 kΩ to 3 6 V 4 4 RL is the load connected...

Page 97: ... for 256xFs is 8 MHz MHz fCK I2S clock frequency Master data 32 bits 64xFs MHz Slave data 32 bits 64xFs DCK I2S clock frequency duty cycle Slave receiver 48KHz 30 70 tr CK I2S clock rise time Capacitive load CL 30pF 8 ns tf CK I2S clock fall time 8 tv WS WS valid time Master mode 4 24 th WS WS hold time Master mode 0 tsu WS WS setup time Slave mode 15 th WS WS hold time Slave mode 0 tsu SD_MR Data...

Page 98: ...t before the first byte Figure 27 I2 S master timing diagram Philips protocol 1 1 Guaranteed by characterization results not tested in production 2 LSB transmit receive of the previously transmitted byte No LSB transmit receive is sent before the first byte QSXW 32 32 WF 6 LQSXW 6 WUDQVPLW 6 UHFHLYH WZ WZ WVX 6 WY 6 B67 WK 6 B67 WK 6 WVX 6 B65 WK 6 B65 06 UHFHLYH LWQ UHFHLYH 6 UHFHLYH 06 WUDQVPLW ...

Page 99: ... Voltage range 3 4 Table 56 ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply 1 8 3 6 V VREF Positive reference voltage 1 8 1 VDDA VREF Negative reference voltage VSSA IVDDA Current on the VDDA input pin 1000 1450 µA IVREF 2 Current on the VREF input pin Peak 400 700 Average 450 VAIN Conversion voltage range 3 0 4 VREF V fS 12 bit sampling rate Direct channels 1 Ms...

Page 100: ...gger conversion latency fADC 16 MHz 156 219 ns 2 5 3 5 1 fADC tSTAB Power up time 3 5 µs 1 The Vref input can be grounded if neither the ADC nor the DAC are used this allows to shut down an external voltage reference 2 The current consumption through VREF is composed of two parameters one constant max 300 µA one variable max 400 µA only during sampling time 2 first conversion pulses So peak consum...

Page 101: ...ic distortion 70 65 ET Total unadjusted error 2 4 V VDDA 3 6 V 1 8 V VREF 2 4 V fADC 4 MHz RAIN 50 Ω TA 40 to 105 C 4 6 5 LSB EO Offset error 2 4 EG Gain error 4 6 ED Differential linearity error 1 2 EL Integral linearity error 1 5 3 ET Total unadjusted error 1 8 V VDDA 2 4 V 1 8 V VREF 2 4 V fADC 4 MHz RAIN 50 Ω TA 40 to 105 C 2 3 LSB EO Offset error 1 1 5 EG Gain error 1 5 2 ED Differential line...

Page 102: ...curacy To remedy this fADC should be reduced DPSOH RI DQ DFWX DO WUDQVIHU FXUYH 7KH LGHDO WUDQVIHU FXUYH QG SRLQW FRUUHODWLRQ OLQH DL H 7 7RWDO XQDGMXVWHG UURU PD LPXP GHYLDWLRQ EHWZHHQ WKH DFWXDO DQG WKH LGHDO WUDQVIHU FXUYHV 2 2IIVHW UURU GHYLDWLRQ EHWZHHQ WKH ILUVW DFWXDO WUDQVLWLRQ DQG WKH ODVW DFWXDO RQH DLQ UURU GHYLDWLRQ EHWZHHQ WKH ODVW LGHDO WUDQVLWLRQ DQG WKH ODVW DFWXDO RQH LIIHUHQWLDO ...

Page 103: ...es Conversion 12 cycles Iref 300µA 700µA MS36686V1 Table 58 Maximum source impedance RAIN max 1 Ts µs RAIN max kΩ Ts cycles fADC 16 MHz 2 Multiplexed channels Direct channels 2 4 V VDDA 3 6 V 1 8 V VDDA 2 4 V 2 4 V VDDA 3 6 V 1 8 V VDDA 2 4 V 0 25 Not allowed Not allowed 0 7 Not allowed 4 0 5625 0 8 Not allowed 2 0 1 0 9 1 2 0 0 8 4 0 3 0 16 1 5 3 0 1 8 6 0 4 5 24 3 6 8 4 0 15 0 10 0 48 6 15 0 10 ...

Page 104: ...A supply VDDA 3 3 V No load middle code 0x800 210 320 No load worst code 0xF1C 320 520 RL 2 Resistive load DAC output buffer ON 5 kΩ CL 2 Capacitive load 50 pF RO Output impedance DAC output buffer OFF 12 16 20 kΩ VDAC_OUT Voltage on DAC_OUT output DAC output buffer ON 0 2 VDDA 0 2 V DAC output buffer OFF 0 5 VREF 1LSB mV DNL 1 Differential non linearity 3 CL 50 pF RL 5 kΩ DAC output buffer ON 1 5...

Page 105: ...CL 50 pF RL 5 kΩ DAC output buffer ON 12 30 LSB No RL CL 50 pF DAC output buffer OFF 8 12 tSETTLING Settling time full scale for a 12 bit code transition between the lowest and the highest input codes till DAC_OUT reaches final value 1LSB CL 50 pF RL 5 kΩ 7 12 µs Update rate Max frequency for a correct DAC_OUT change 95 of final value with 1 LSB variation in the input code CL 50 pF RL 5 kΩ 1 Msps ...

Page 106: ...lope of the transfer function and measured slope computed from code 0x000 and 0xFFF when buffer is OFF and from code giving 0 2 V and VDDA 0 2 V when buffer is ON 8 In buffered mode the output can overshoot above the final value for low input code starting from min value 5 XIIHUHG 1RQ EXIIHUHG B287 XIIHU ELW GLJLWDO WR DQDORJ FRQYHUWHU AI 6 Table 60 Operational amplifier characteristics Symbol Par...

Page 107: ... CL Capacitive load 50 pF VOHSAT High saturation voltage Normal mode ILOAD max or RL min VDD 100 mV Low power mode VDD 50 VOLSAT Low saturation voltage Normal mode 100 Low power mode 50 ϕm Phase margin 60 GM Gain margin 12 dB tOFFTRIM Offset trim time during calibration minimum time needed between two steps to have 1 mV accuracy 1 ms tWAKEUP Wakeup time Normal mode CL 50 pf RL 4 kΩ 10 µs Low power...

Page 108: ...1 Average slope 1 48 1 61 1 75 mV C V110 Voltage at 110 C 5 C 2 2 Measured at VDD 3 V 10 mV V110 ADC conversion result is stored in the TS_CAL2 byte 612 626 8 641 5 mV IDDA TEMP 3 Current consumption 3 4 6 µA tSTART 3 3 Guaranteed by design not tested in production Startup time 10 µs TS_temp 3 ADC sampling time when reading the temperature 4 Table 63 Comparator 1 characteristics Symbol Parameter C...

Page 109: ...2 input voltage range 0 VDDA V tSTART Comparator startup time Fast mode 15 20 µs Slow mode 20 25 td slow Propagation delay 2 in slow mode 2 The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input the non inverting input set to the reference 1 65 V VDDA 2 7 V 1 8 3 5 2 7 V VDDA 3 6 V 2 5 6 td fast Propagation delay 2 in fast mode 1 65 V VDDA 2 7 V 0 8 2 2 7 V VD...

Page 110: ...oltage 6 3 4 VLCD7 LCD internal reference voltage 7 3 55 Cext VLCD external capacitance 0 1 2 µF ILCD 1 1 LCD enabled with 3 V internal step up active 1 8 duty 1 4 bias division ratio 64 all pixels active no LCD connected Supply current at VDD 2 2 V 3 3 µA Supply current at VDD 3 0 V 3 1 RHtot 2 2 Guaranteed by design not tested in production Low drive resistive network overall value 5 28 6 6 7 92...

Page 111: ...rent grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark 7 1 1 LQFP100 14 x 14 mm 100 pin low profile quad flat package information Figure 32 LQFP100 14 x 14 mm 100 pin low profile quad flat package outline 1 Drawing is not to scale E 4 4 0 5 0 MM 3 4 0 CCC...

Page 112: ...mal digits Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 c 0 090 0 200 0 0035 0 0079 D 15 800 16 000 16 200 0 6220 0 6299 0 6378 D1 13 800 14 000 14 200 0 5433 0 5512 0 5591 D3 12 000 0 4724 E 15 800 16 000 16 200 0 6220 0 6299 0 6378 E1 13 800 14 000 14 200 0 5433 0 5512 0 5591 E3 12 000 0 472...

Page 113: ...panied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification...

Page 114: ...C 114 135 DocID022799 Rev 10 7 1 2 LQFP64 10 x 10 mm 64 pin low profile quad flat package information Figure 35 LQFP64 10 x 10 mm 64 pin low profile quad flat package outline 1 Drawing is not to scale B0 B9 6 7 1 3 1 FFF E F 17 7 21 3 1 H 8 3 1 PP ...

Page 115: ...cimal digits Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 c 0 090 0 200 0 0035 0 0079 D 11 800 12 000 12 200 0 4646 0 4724 0 4803 D1 9 800 10 000 10 200 0 3858 0 3937 0 4016 D3 7 500 0 2953 E 11 800 12 000 12 200 0 4646 0 4724 0 4803 E1 9 800 10 000 10 200 0 3858 0 3937 0 4016 E3 7 500 0 2953 ...

Page 116: ...nied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification a...

Page 117: ... STM32L152xC Package characteristics 134 7 1 3 LQFP48 7 x 7 mm 48 pin low profile quad flat package information Figure 38 LQFP48 7 x 7 mm 48 pin low profile quad flat package outline 1 Drawing is not to scale 6 0 4 4 CCC MM 5 0 B C E 3 4 0 ...

Page 118: ...o 4 decimal digits Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 c 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 500 0 2165 E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 500 0 2165 e 0 ...

Page 119: ...anied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification ...

Page 120: ...ge outline 1 Drawing is not to scale 2 All leads pads should also be soldered to the PCB to improve the lead pad solder joint life 3 There is an exposed die pad on the underside of the UFQFPN package It is recommended to connect and solder this back side pad to PCB ground B0 B9 3LQ LGHQWLILHU ODVHU PDUNLQJ DUHD SRVHG SDG DUHD HWDLO 5 W S SLQ FRUQHU 6HDWLQJ SODQH E H GGG HWDLO 7 ...

Page 121: ...eters inches 1 1 Values in inches are converted from mm and rounded to 4 decimal digits Min Typ Max Min Typ Max A 0 500 0 550 0 600 0 0197 0 0217 0 0236 A1 0 000 0 020 0 050 0 0000 0 0008 0 0020 D 6 900 7 000 7 100 0 2717 0 2756 0 2795 E 6 900 7 000 7 100 0 2717 0 2756 0 2795 D2 5 500 5 600 5 700 0 2165 0 2205 0 2244 E2 5 500 5 600 5 700 0 2165 0 2205 0 2244 L 0 300 0 400 0 500 0 0118 0 0157 0 019...

Page 122: ...nied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification a...

Page 123: ...s 1 Min Typ Max Min Typ Max A 0 460 0 530 0 600 0 0181 0 0209 0 0236 A1 0 050 0 080 0 110 0 0020 0 0031 0 0043 A2 0 400 0 450 0 500 0 0157 0 0177 0 0197 A3 0 080 0 130 0 180 0 0031 0 0051 0 0071 A4 0 270 0 320 0 370 0 0106 0 0126 0 0146 b 0 200 0 250 0 300 0 0079 0 0098 0 0118 D 6 950 7 000 7 050 0 2736 0 2756 0 2776 D1 5 450 5 500 5 550 0 2146 0 2165 0 2185 E 6 950 7 000 7 050 0 2736 0 2756 0 277...

Page 124: ...consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity eee 0 150 0 0059 fff 0 050 0 0020 1 Values in inches are converted from mm and rounded to 4 decimal digits Table 70 UFBGA100 ...

Page 125: ... pitch wafer level chip size package information Figure 46 WLCSP63 0 400 mm pitch wafer level chip size package outline 1 Drawing is not to scale OTTOM VIEW UMB SIDE ALL LOCATION 3IDE VIEW 4OP VIEW 7AFER BACK 3IDE REFERENCE LOCATION ETAIL ROTATED ETAIL 3EATING PLANE RONT VIEW E E E E UMP BBB BBB FFF 5 ...

Page 126: ... rounded to 4 decimal digits Min Typ Max Min Typ Max A 0 540 0 570 0 600 0 0213 0 0224 0 0236 A1 0 190 0 0075 A2 0 380 0 0150 A3 0 025 0 0010 Øb 0 240 0 270 0 300 0 0094 0 0106 0 0118 D 3 193 3 228 3 263 0 1257 0 1271 0 1285 E 4 129 4 164 4 199 0 1626 0 1639 0 1653 e 0 400 0 0157 e1 2 400 0 0945 e2 3 200 0 1260 F 0 414 0 0163 G 0 482 0 0190 aaa 0 100 0 0039 bbb 0 100 0 0039 ccc 0 100 0 0039 ddd 0 ...

Page 127: ...companied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualificat...

Page 128: ...imum chip internal power PI O max represents the maximum power dissipation on output pins where PI O max Σ VOL IOL Σ VDD VOH IOH taking into account the actual VOL IOL and VOH IOH of the I Os at low and high level in the application Table 72 Thermal characteristics Symbol Parameter Value Unit ΘJA Thermal resistance junction ambient UFBGA100 7 x 7 mm 59 C W Thermal resistance junction ambient LQFP1...

Page 129: ...suffix 7 7 2 1 Reference document JESD51 2 Integrated Circuits Thermal Test Method Environment Conditions Natural Convection Still Air Available from www jedec org D ϯϭϰϬϱsϱ Ϭ ϬϬ ϱϬϬ ϬϬ Ϭ ŽƌďŝĚĚĞŶ ĂƌĞĂ d х d ŵĂǆ 4 3 PP 63 8 PP 4 3 PP 8 4 31 PP 4 3 PP 7HPSHUDWXUH 3 P 06Y 9 RUELGGHQ DUHD 7 7 PD 4 3 PP 63 8 PP 4 3 PP 8 4 31 PP 4 3 PP 7HPSHUDWXUH 3 P ...

Page 130: ...Device family STM32 ARM based 32 bit microcontroller Product type L Low power Device subfamily 151 Devices without LCD 152 Devices with LCD Pin count C 48 pins U 63 pins R 64 pins V 100 pins Flash memory size C 256 Kbytes of Flash memory Package H BGA T LQFP Y WLCSP U UFQFPN Temperature range 6 Industrial temperature range 40 to 85 C 7 Industrial temperature range 40 to 105 C Options No character ...

Page 131: ...nual in footnote 5 Changed I2C1_SMBAI into I2C1_SMBA in Table 10 STM32L15xxC pin definitions Modified PB10 11 12 for AFIO4 alternate function and replaced LBAR by NADV for AFIO12 in Table 10 Alternate function input output Removed caution note below Figure 8 Power supply scheme Added Note 2 in Table 15 Embedded reset and power control block characteristics Updated Table 14 General operating condit...

Page 132: ...haracteristics 02 Sep 2013 4 Removed UFBGA132 and LQFP144 packages Removed first sentence in Section I2C interface characteristics Added Section Table 5 VLCD rail decoupling Added VRAIL functions in Table 9 STM32L15xxC pin definitions Updated PH0 OSC_IN and PH1 OSC_OUT type in Table 9 STM32L15xxC pin definitions Added Table 6 1 7 Optional LCD power supply scheme Updated consumption data in Table 6...

Page 133: ...lock characteristics Moved Figure 12 High speed external clock source AC timing diagram after Table 38 High speed external user clock characteristics Updated Table 40 HSE oscillator characteristics Updated Section 6 3 12 Electrical sensitivity characteristics title Updated Section 6 3 13 I O current injection characteristics Updated Table 61 I O current injection susceptibility and added footnote ...

Page 134: ... consumption in Run mode code with data processing running from Flash Updated Section 6 3 1 General operating conditions Updated Table 80 DAC characteristics Added marking for LQFP48 UFQFPN48 packages Updated Table 66 NRST pin characteristics Updated Table 63 I O static characteristics 16 May 2014 8 Updated IIO in Table 12 Current characteristics Updated conditions in Table 44 Output voltage chara...

Page 135: ...gement Purchasers are solely responsible for the choice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to any intellectual property right is granted by ST herein Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for su...

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