DocID023833 Rev 5
STM32F42xx and STM32F43xx
STM32F42xx and STM32F43xx silicon limitations
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This limitation will be fixed in next silicon revision.
2.8.7
FMC dynamic and static banks switching
Description
The dynamic and static banks cannot be accessed concurrently.
Workaround
Do not use dynamic and static banks at the same time. The SDRAM device must be in self-
refresh before switching to the static memory mapped on the NOR/PSRAM or NAND/PC-
Card controller. Before switching from static memory to SDRAM, issue a Normal command
to wake-up the device from self-refresh mode.
2.9
SDIO peripheral limitations
2.9.1
SDIO HW flow control
Description
When enabling the HW flow control by setting bit 14 of the SDIO_CLKCR register to ‘1’,
glitches can occur on the SDIOCLK output clock resulting in wrong data to be written into
the SD/MMC card or into the SDIO device. As a consequence, a CRC error will be reported
to the SD/SDIO MMC host interface (DCRCFAIL bit set to ‘1’ in SDIO_STA register).
Workaround
None.
Note:
Do not use the HW flow control. Overrun errors (Rx mode) and FIFO underrun (Tx mode)
should be managed by the application software.
2.9.2
Wrong CCRCFAIL status after a response without CRC is received
Description
The CRC is calculated even if the response to a command does not contain any CRC field.
As a consequence, after the SDIO command IO_SEND_OP_COND (CMD5) is sent, the
CCRCFAIL bit of the SDIO_STA register is set.
Workaround
The CCRCFAIL bit in the SDIO_STA register shall be ignored by the software. CCRCFAIL
must be cleared by setting CCRCFAILC bit of the SDIO_ICR register after reception of the
response to the CMD5 command.