DocID023833 Rev 5
STM32F42xx and STM32F43xx
STM32F42xx and STM32F43xx silicon limitations
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Workaround
Two workarounds could be applicable:
•
Ensure a delay of four TX_CLK/RX_CLK clock cycles between the successive write
operations to the same register.
•
Make several successive write operations without delay, then read the register when all
the operations are complete, and finally reprogram it after a delay of four
TX_CLK/RX_CLK clock cycles.
2.8
FMC peripheral limitation
2.8.1
Dummy read cycles inserted when reading synchronous memories
Description
When performing a burst read access to a synchronous memory, two dummy read accesses
are performed at the end of the burst cycle whatever the type of AHB burst access.
However, the extra data values which are read are not used by the FMC and there is no
functional failure.
Workaround
None.
2.8.2 FMC
synchronous
mode
and NWAIT signal disabled
Description
When the FMC synchronous mode operates with the NWAIT signal disabled, if the polarity
(WAITPOL in the FMC_BCRx register) of the NWAIT signal is identical to that of the NWAIT
input signal level, the system hangs and no fault is generated.
Workaround
PD6 (NWAIT signal) must not be connected to AF12 and the NWAIT polarity must be
configured to active high (set WAITPOL bit to 1 in FMC_BCRx register).
2.8.3
Read access to a non-initialized FMC_SDRAM bank
Description
When a read access is performed to an SDRAM bank while the SDRAM controller is not yet
initialized, the system hangs and no fault is generated.
Workaround
Read access to an SDRAM bank must be performed only when the SDRAM controller
initialization is complete.