STMicroelectronics STM32F427, Manual, Page: 14 / 36

STM32F42xx and STM32F43xx silicon limitations STM32F42xx and STM32F43xx
14/36 DocID023833 Rev 5
2.3.2 Start cannot be generated after a misplaced Stop
Description
If a master generates a misplaced Stop on the bus (bus error), the peripheral cannot
generate a Start anymore.
Workaround
In the I²C standard, it is allowed to send a Stop only at the end of the full byte (8 bits +
acknowledge), so this scenario is not allowed. Other derived protocols like CBUS allow it,
but they are not supported by the I²C peripheral.
A software workaround consists in asserting the software reset using the SWRST bit in the
I2C_CR1 control register.
2.3.3 Mismatch on the “Setup time for a repeated Start condition” timing
parameter
Description
In case of a repeated Start, the “Setup time for a repeated Start condition” (named Tsu;sta in
the I²C specification) can be slightly violated when the I²C operates in Master Standard
mode at a frequency between 88 kHz and 100 kHz.
The limitation can occur only in the following configuration:
•
in Master mode
•
in Standard mode at a frequency between 88 kHz and 100 kHz (no limitation in Fast-
mode)
•
SCL rise time:
– If the slave does not stretch the clock and the SCL rise time is more than 300 ns (if
the SCL rise time is less than 300 ns, the limitation cannot occur)
– If the slave stretches the clock
The setup time can be violated independently of the APB peripheral frequency.
Workaround
Reduce the frequency down to 88 kHz or use the I²C Fast-mode, if supported by the slave.
2.3.4 Data valid time (t
VD;DAT
) violated without the OVR flag being set
Description
The data valid time (t
VD;DAT
, t
VD;ACK
) described by the I²C standard can be violated (as well
as the maximum data hold time of the current data (t
HD;DAT
)) under the conditions described
below. This violation cannot be detected because the OVR flag is not set (no transmit buffer
underrun is detected).
This limitation can occur only under the following conditions:
•
in Slave transmit mode
•
with clock stretching disabled (NOSTRETCH=1)
•
if the software is late to write the DR data register, but not late enough to set the OVR
flag (the data register is written before)