DocID018909 Rev 11
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RM0090
Embedded Flash memory interface
112
3.9.12 Flash
interface register map
Table 19. Flash register map and reset values
(STM32F405xx/07xx and STM32F415xx/17xx)
Offset
Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x00
FLASH_ACR
Reserved
DCRST
ICRST
DCEN
ICE
N
PRFTEN
Reserved
LATENCY
[2:0]
Reset value
0
0
0 0
0
0
0
0
0x04
FLASH_
KEYR
KEY[31:16]
KEY[15:0]
Reset value
0
0 0
0
0
0 0
0
0
0 0
0
0
0 0
0
0
0 0
0
0
0 0
0 0 0 0 0 0
0
0
0
0x08
FLASH_OPT
KEYR
OPTKEYR[31:16]
OPTKEYR[15:0]
Reset value
0
0 0
0
0
0 0
0
0
0 0
0
0
0 0
0
0
0 0
0
0
0 0
0 0 0 0 0 0
0
0
0
0x0C
FLASH_SR
Reserved
BS
Y
Reserved
PGS
E
RR
PGP
E
RR
PGA
E
RR
WRP
E
RR
Reserved
OPE
R
R
EOP
Reset value
0
0 0 0 0
0
0
0x10
FLASH_CR
LO
C
K
Reserved
EO
PI
E
Reserved
STR
T
Reserved
PSIZ
E[1:0
]
Reser
ve
d
SNB[3:0]
ME
R
SER
PG
Reset value
1
0
0
0
0
0 0 0 0
0
0
0x14
FLASH_
OPTCR
Reserved
nWRP[11:0]
RDP[7:0]
nRS
T
_S
TDBY
nRST_ST
O
P
WDG
_
SW
Reserved
BOR_
LEV[
1:
0]
O
P
TSTR
T
OP
T
L
OCK
Reset value
1
1 1
1
1
1 1
1
1
1 1
1
1
0 1
0
1
0 1
0 1 1 1
1
1
0
1
Table 20. Flash register map and reset values (STM32F42xxx and STM32F43xxx)
Offset
Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x00
FLASH_ACR
Reserved
DCR
S
T
IC
RST
DCEN
ICE
N
PRFTEN
Reserved
LATENCY[3:0]
Reset value
0 0 0 0 0
0
0
0
0
0x04
FLASH_KEYR
KEY[31:16]
KEY[15:0]
Reset value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
0
0x08
FLASH_
OPTKEYR
OPTKEYR[31:16]
OPTKEYR[15:0]
Reset value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
0
0x0C
FLASH_SR
Reserved
BS
Y
Reserved
RD
E
R
R
PGS
E
RR
PGP
E
RR
PGA
E
RR
WRP
E
RR
Reserved
OPE
R
R
EOP
Reset value
0
0 0 0 0 0
0
0