STMicroelectronics STM32F031C4 Manual Download Page 78

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Electrical characteristics

STM32F031x4 STM32F031x6

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DocID025743 Rev 3

Figure 24. ADC accuracy characteristics

Figure 25. Typical connection diagram using the ADC

Refer to

Table 50: ADC characteristics

for the values of R

AIN

, R

ADC

and C

ADC

parasitic

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

pad capacitance (roughly 7

pF). A high C

parasitic

value will downgrade conversion accuracy. To remedy

this, f

ADC

should be reduced.

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure 12: Power supply

scheme

. The 10 nF capacitor should be ceramic (good quality) and it should be placed as

close as possible to the chip.

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Summary of Contents for STM32F031C4

Page 1: ...h deadtime generation and emergency stop 1 x 32 bit and 1 x 16 bit timer with up to 4 IC OC usable for IR control decoding 1 x 16 bit timer with 2 IC OC 1 OCN deadtime generation and emergency stop 1 x 16 bit timer with IC OC and OCN deadtime generation emergency stop and modulator gate for IR control 1 x 16 bit timer with 1 IC OC Independent and system watchdog timers SysTick timer 24 bit downcou...

Page 2: ...6 3 9 1 Nested vectored interrupt controller NVIC 16 3 9 2 Extended interrupt event controller EXTI 16 3 10 Analog to digital converter ADC 17 3 10 1 Temperature sensor 17 3 10 2 Internal voltage reference VREFINT 17 3 10 3 VBAT battery voltage monitoring 18 3 11 Timers and watchdogs 18 3 11 1 Advanced control timer TIM1 18 3 11 2 General purpose timers TIM2 3 TIM14 16 17 19 3 11 3 Independent wat...

Page 3: ... at power up power down 43 6 3 3 Embedded reset and power control block characteristics 43 6 3 4 Embedded reference voltage 44 6 3 5 Supply current characteristics 45 6 3 6 Wakeup time from low power mode 55 6 3 7 External clock source characteristics 56 6 3 8 Internal clock source characteristics 62 6 3 9 PLL characteristics 64 6 3 10 Memory characteristics 65 6 3 11 EMC characteristics 65 6 3 12...

Page 4: ...mation 94 7 4 UFQFPN28 package information 97 7 5 WLCSP25 package information 100 7 6 WLCSP25 package information 100 7 7 TSSOP20 package information 103 7 8 Thermal characteristics 106 7 8 1 Reference document 106 7 8 2 Selecting the product temperature range 107 8 Part numbering 109 9 Revision history 110 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 微可Vicor 值得信赖的元器件供应商 http www vicor top ...

Page 5: ...e 44 Table 23 Typical and maximum current consumption from the VDD supply at VDD 3 6 V 46 Table 24 Typical and maximum current consumption from the VDDA supply 47 Table 25 Typical and maximum current consumption in Stop and Standby modes 48 Table 26 Typical and maximum current consumption from the VBAT supply 49 Table 27 Typical current consumption code executing from Flash running from HSE 8 MHz ...

Page 6: ...age mechanical data 88 Table 62 LQFP32 32 pin 7 x 7 mm low profile quad flat package mechanical data 92 Table 63 UFQFPN32 32 pin 5x5 mm 0 5 mm pitch ultra thin fine pitch quad flat package mechanical data 95 Table 64 UFQFPN28 28 lead 4x4 mm 0 5 mm pitch ultra thin fine pitch quad flat package mechanical data 97 Table 65 WLCSP25 25 ball 2 423 x 2 325 mm 0 4 mm pitch wafer level chip scale package m...

Page 7: ...racy characteristics 78 Figure 25 Typical connection diagram using the ADC 78 Figure 26 SPI timing diagram slave mode and CPHA 0 83 Figure 27 SPI timing diagram slave mode and CPHA 1 83 Figure 28 SPI timing diagram master mode 84 Figure 29 I2S slave timing diagram Philips protocol 85 Figure 30 I2S master timing diagram Philips protocol 86 Figure 31 LQFP48 48 pin 7 x 7 mm low profile quad flat pack...

Page 8: ...ckage recommended footprint 101 Figure 45 WLCSP25 marking example package top view 102 Figure 46 TSSOP20 20 lead thin shrink small outline 6 5 x 4 4 mm 0 65 mm pitch package outline 103 Figure 47 TSSOP20 20 lead thin shrink small outline 6 5 x 4 4 mm 0 65 mm pitch package footprint 104 Figure 48 TSSOP20 marking example package top view 105 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 微可Vico...

Page 9: ...is document should be read in conjunction with the STM32F0xxxx reference manual RM0091 The reference manual is available from the STMicroelectronics website www st com For information on the ARM Cortex M0 core please refer to the Cortex M0 Technical Reference Manual available from the www arm com website 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 微可Vicor 值得信赖的元器件供应商 http www vicor top 021...

Page 10: ... the complete range of STM32F031x4 x6 peripherals proposed These features make the STM32F031x4 x6 microcontrollers suitable for a wide range of applications such as application control and user interfaces hand held equipment A V receivers and digital TV PC peripherals gaming and GPS platforms industrial applications PLCs inverters printers scanners alarm systems video intercoms and HVACs Table 2 S...

Page 11: ...3 5 6833 9 9 9 7 9 WR 9 5 7 76 576 DV 19 63 6 RQWUROOHU 9 683 59 6 21 39 5HVHW QW 9 3 325 7 03 5 57 5 6 7 2 21752 3 50 287 6HULDO LUH HEXJ 0 62 0 3 3 3 FK 75 DV FKDQQHO DV 9 5 6 0 86 57 FKDQQHO FRPSO 5 DV FKDQQHO FRPSO 5 DV FRQWUROOHU 65 0 6 6 P IRU 0 5B287 DV 0 8 GHFRGHU 06 9 7 0 5 7 0 5 7 0 5 7 0 5 7 0 5 7 0 5 86 57 3 2 SRUW 3 2 SRUW 3 2 SRUW 3 2 SRUW ELW B 1 9 7HPS VHQVRU 966 9 5 6 0 5 6 6 026 ...

Page 12: ...accessed read write at CPU clock speed with 0 wait states and featuring embedded parity checking with exception generation for fail critical applications The non volatile memory is divided into two arrays 16 to 32 Kbytes of embedded Flash memory for programs and data Option bytes The option bytes are used to write protect the memory with 4 KB granularity and or readout protect the whole memory wit...

Page 13: ...wer pins refer to Figure 12 Power supply scheme 3 5 2 Power supply supervisors The device has integrated power on reset POR and power down reset PDR circuits They are always active and ensure proper operation above a threshold of 2 V The device remains in reset mode when the monitored supply voltage is below a specified threshold VPOR PDR without the need for an external reset circuit The POR moni...

Page 14: ...normal mode before the clock is provided to the given peripheral Standby mode The Standby mode is used to achieve the lowest power consumption The internal voltage regulator is switched off so that the entire 1 8 V domain is powered off The PLL the HSI RC and the HSE crystal oscillators are also switched off After entering Standby mode SRAM and register contents are lost except for registers in th...

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Page 16: ...t controller NVIC The STM32F0xx family embeds a nested vectored interrupt controller able to handle up to 32 maskable interrupt channels not including the 16 interrupt lines of Cortex M0 and 4 priority levels Closely coupled NVIC gives low latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of int...

Page 17: ...uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only To improve the accuracy of the temperature sensor measurement each device is individually factory calibrated by ST The temperature sensor factory calibration data are stored by ST in the system memory area accessible in read only mode 3 10 2 Internal voltage reference VREFINT The internal vol...

Page 18: ...t can also be seen as a complete general purpose timer The four independent channels can be used for Input capture Output compare PWM generation edge or center aligned modes One pulse mode output If configured as a standard 16 bit timer it has the same features as the TIMx timer If configured as the 16 bit PWM generator it has full modulation capability 0 100 The counter can be frozen in debug mod...

Page 19: ... 12 input captures output compares PWMs on the largest packages The TIM2 and TIM3 general purpose timers can work together or with the TIM1 advanced control timer via the Timer Link feature for synchronization or event chaining TIM2 and TIM3 both have independent DMA request generation These timers are capable of handling quadrature incremental encoder signals and the digital outputs from 1 to 3 h...

Page 20: ...five backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin The backup registers are five 32 bit registers used to store 20 bytes of user application data when VDD power is not present They are not reset by a system or power reset or when the device wakes up from Standby mode The RTC is an independent BCD timer counter Its main fea...

Page 21: ... timeouts verifications and ALERT protocol management I2C1 also has a clock domain independent from the CPU clock allowing the I2C1 to wake up the MCU from Stop mode on address match The I2C interface can be served by the DMA controller Table 6 Comparison of I2C analog and digital filters Analog filter Digital filter Pulse width of suppressed spikes 50 ns Programmable length from 1 to 15 I2C perip...

Page 22: ...lity and auto baud rate feature and has a clock domain independent from the CPU clock allowing to wake up the MCU from Stop mode The USART interface can be served by the DMA controller 1 X supported Table 8 STM32F031x4 x6 USART implementation USART modes features 1 1 X supported USART1 Hardware flow control for modem X Continuous communication using DMA X Multiprocessor communication X Synchronous...

Page 23: ...an be configured to transfer 16 and 24 or 32 bits with 16 bit or 32 bit data resolution and synchronized by a specific signal Audio sampling frequency from 8 kHz up to 192 kHz can be set by an 8 bit programmable linear prescaler When operating in master mode it can output a clock for an external audio component at 256 times the sampling frequency 3 16 Serial wire debug port SW DP An ARM SW DP inte...

Page 24: ...in package pinout 4 3 3 3 3 3 3 3 3 3 3 3 966 9 3 3 3 3 3 3 3 3 3 3 3 3 9 7 1567 966 9 3 3 3 9 966 3 3 227 3 3 3 3 3 3 3 06 9 3 3 26 B 1 3 26 B 1 3 26 B287 3 26 B287 06 9 4 3 3 3 3 3 3 3 3 966 3 3 3 3 3 3 3 9 1567 9 3 3 3 966 227 3 3 3 3 3 3 3 26 B 1 3 26 B287 9 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 ...

Page 25: ...igure 6 UFQFPN28 28 pin package pinout 3 9 1567 3 3 3 3 3 3 3 9 3 3 3 3 3 3 3 227 3 3 3 06 9 9 3 3 3 3 3 3 3 26 B 1 3 26 B287 3 966 966 3 3 3 3 3 3 3 227 9 966 3 3 3 3 3 3 3 3 3 3 06 9 3 3 3 1567 3 9 3 26 B 1 3 26 B287 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 ...

Page 26: ...ll package ballout bump side Figure 8 TSSOP20 20 pin package pinout 06Y 9 3 3 1567 9 3 227 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 9 966 06 9 3 26 B 1 227 3 26 B287 1567 9 3 3 9 3 3 3 3 966 3 3 3 3 3 3 3 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 ...

Page 27: ...esistor Notes Unless otherwise specified by a note all I Os are set as floating inputs during and after reset Pin functions Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected enabled through peripheral registers Table 11 Pin definitions Pin number Pin name function after reset Pin type I O structure Notes Pin functions LQFP48 LQFP32 ...

Page 28: ...a TIM2_CH4 USART1_RX ADC_IN3 14 10 10 10 B3 10 PA4 I O TTa SPI1_NSS I2S1_WS TIM14_CH1 USART1_CK ADC_IN4 15 11 11 11 C3 11 PA5 I O TTa SPI1_SCK I2S1_CK TIM2_CH1_ETR ADC_IN5 16 12 12 12 D3 12 PA6 I O TTa SPI1_MISO I2S1_MCK TIM3_CH1 TIM1_BKIN TIM16_CH1 EVENTOUT ADC_IN6 17 13 13 13 E4 13 PA7 I O TTa SPI1_MOSI I2S1_SD TIM3_CH2 TIM14_CH1 TIM1_CH1N TIM17_CH1 EVENTOUT ADC_IN7 Table 11 Pin definitions cont...

Page 29: ...I1_NSS 26 PB13 I O FT TIM1_CH1N SPI1_SCK 27 PB14 I O FT TIM1_CH2N SPI1_MISO 28 PB15 I O FT TIM1_CH3N SPI1_MOSI RTC_REFIN 29 18 18 18 D2 PA8 I O FT USART1_CK TIM1_CH1 EVENTOUT MCO 30 19 19 19 C1 17 PA9 I O FTf USART1_TX TIM1_CH2 I2C1_SCL 31 20 20 20 B1 18 PA10 I O FTf USART1_RX TIM1_CH3 TIM17_BKIN I2C1_SDA Table 11 Pin definitions continued Pin number Pin name function after reset Pin type I O stru...

Page 30: ...6 24 PB3 I O FT SPI1_SCK I2S1_CK TIM2_CH2 EVENTOUT 40 27 27 25 PB4 I O FT SPI1_MISO I2S1_MCK TIM3_CH1 EVENTOUT 41 28 28 26 C2 PB5 I O FT SPI1_MOSI I2S1_SD I2C1_SMBA TIM16_BKIN TIM3_CH2 42 29 29 27 B2 PB6 I O FTf I2C1_SCL USART1_TX TIM16_CH1N 43 30 30 28 A3 PB7 I O FTf I2C1_SDA USART1_RX TIM17_CH1N Table 11 Pin definitions continued Pin number Pin name function after reset Pin type I O structure No...

Page 31: ... then depends on the content of the RTC registers which are not reset by the system reset For details on how to manage these GPIOs refer to the RTC domain and RTC register descriptions in the reference manual 3 On the LQFP32 package PB2 and PB8 should be treated as unconnected pins even when they are not available on the package they are not forced to a defined level by hardware 4 After reset thes...

Page 32: ... PA5 SPI1_SCK I2S1_CK TIM2_CH1_ ETR PA6 SPI1_MISO I2S1_MCK TIM3_CH1 TIM1_BKIN TIM16_CH1 EVENTOUT PA7 SPI1_MOSI I2S1_SD TIM3_CH2 TIM1_CH1N TIM14_CH1 TIM17_CH1 EVENTOUT PA8 MCO USART1_CK TIM1_CH1 EVENTOUT PA9 USART1_TX TIM1_CH2 I2C1_SCL PA10 TIM17_BKIN USART1_RX TIM1_CH3 I2C1_SDA PA11 EVENTOUT USART1_CTS TIM1_CH4 PA12 EVENTOUT USART1_RTS TIM1_ETR PA13 SWDIO IR_OUT PA14 SWCLK USART1_TX PA15 SPI1_NSS ...

Page 33: ...PB4 SPI1_MISO I2S1_MCK TIM3_CH1 EVENTOUT PB5 SPI1_MOSI I2S1_SD TIM3_CH2 TIM16_BKIN I2C1_SMBA PB6 USART1_TX I2C1_SCL TIM16_CH1N PB7 USART1_RX I2C1_SDA TIM17_CH1N PB8 I2C1_SCL TIM16_CH1 PB9 IR_OUT I2C1_SDA TIM17_CH1 EVENTOUT PB10 I2C1_SCL TIM2_CH3 PB11 EVENTOUT I2C1_SDA TIM2_CH4 PB12 SPI1_NSS EVENTOUT TIM1_BKIN PB13 SPI1_SCK TIM1_CH1N PB14 SPI1_MISO TIM1_CH2N PB15 SPI1_MOSI TIM1_CH3N 微可Vicor 值得信赖的元器...

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Page 35: ...d 0x4002 1000 0x4002 13FF 1 KB RCC 0x4002 0400 0x4002 0FFF 3 KB Reserved 0x4002 0000 0x4002 03FF 1 KB DMA 0x4001 8000 0x4001 FFFF 32 KB Reserved APB 0x4001 5C00 0x4001 7FFF 9KB Reserved 0x4001 5800 0x4001 5BFF 1KB DBGMCU 0x4001 4C00 0x4001 57FF 3KB Reserved 0x4001 4800 0x4001 4BFF 1KB TIM17 0x4001 4400 0x4001 47FF 1KB TIM16 0x4001 3C00 0x4001 43FF 2KB Reserved 0x4001 3800 0x4001 3BFF 1KB USART1 0x...

Page 36: ...3FF 1KB IWDG 0x4000 2C00 0x4000 2FFF 1KB WWDG 0x4000 2800 0x4000 2BFF 1KB RTC 0x4000 2400 0x4000 27FF 1KB Reserved 0x4000 2000 0x4000 23FF 1KB TIM14 0x4000 0800 0x4000 1FFF 6KB Reserved 0x4000 0400 0x4000 07FF 1KB TIM3 0x4000 0000 0x4000 03FF 1KB TIM2 Table 14 STM32F031x4 x6 peripheral register boundary addresses continued Bus Boundary address Size Peripheral 微可Vicor 值得信赖的元器件供应商 http www vicor top...

Page 37: ... value plus or minus three times the standard deviation mean 3 6 1 2 Typical values Unless otherwise specified typical data are based on TA 25 C VDD VDDA 3 3 V They are given only as design guidelines and are not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range where 95 of the devices have an e...

Page 38: ... shown above These capacitors must be placed as close as possible to or below the appropriate pins on the underside of the PCB to ensure the good functionality of the device 9 HYHO VKLIWHU 2 ORJLF HUQHO ORJLF 38 LJLWDO 0HPRULHV 6 57 DNH XS ORJLF 1 287 5HJXODWRU 3 2V Q 966 9 9 25 3RZHU VZLWFK 9 2 QDORJ 5 V 3 95 95 9 Q 9 966 9 9 7 06Y 9 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 微可Vicor 值得信...

Page 39: ...031x6 Electrical characteristics 86 6 1 7 Current consumption measurement Figure 13 Current consumption measurement scheme 06 9 9 7 9 9 B9 7 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 ...

Page 40: ...V VDDA VSS External analog supply voltage 0 3 4 0 V VDD VDDA Allowed voltage difference for VDD VDDA 0 4 V VBAT VSS External backup supply voltage 0 3 4 0 V VIN 2 2 VIN maximum must always be respected Refer to Table 16 Current characteristics for the maximum allowed injected current values Input voltage on FT and FTf pins VSS 0 3 VDDIOx 4 0 3 3 Valid only if the internal pull up pull down resisto...

Page 41: ...permitted range 2 This current consumption must be correctly distributed over all I Os and control pins The total output current must not be sunk sourced between two consecutive power supply pins referring to high pin count QFP packages 3 A positive injection is induced by VIN VDDIOx while a negative injection is induced by VIN VSS IINJ PIN must never be exceeded Refer to Table 15 Voltage characte...

Page 42: ...ix 6 or TA 105 C for suffix 7 2 LQFP48 364 mW UFQFPN32 526 LQFP32 357 UFQFPN28 169 WLCSP25 267 TSSOP20 182 TA Ambient temperature for the suffix 6 version Maximum power dissipation 40 85 C Low power dissipation 3 40 105 Ambient temperature for the suffix 7 version Maximum power dissipation 40 105 C Low power dissipation 3 40 125 TJ Junction temperature range Suffix 6 version 40 105 C Suffix 7 vers...

Page 43: ...1 The PDR detector monitors VDD and also VDDA if kept enabled in the option bytes The POR detector monitors only VDD Power on power down reset threshold Falling edge 2 2 The product behavior is guaranteed by design down to the minimum VPOR PDR value 1 80 1 88 1 96 3 3 Data based on characterization results not tested in production V Rising edge 1 84 3 1 92 2 00 V VPDRhyst PDR hysteresis 40 mV tRST...

Page 44: ...rrent consumption 0 15 0 26 1 µA 1 Guaranteed by design not tested in production Table 21 Programmable voltage detector characteristics continued Symbol Parameter Conditions Min Typ Max Unit Table 22 Embedded internal reference voltage Symbol Parameter Conditions Min Typ Max Unit VREFINT Internal reference voltage 40 C TA 105 C 1 16 1 2 1 25 V 40 C TA 85 C 1 16 1 2 1 24 1 1 Data based on character...

Page 45: ...med with a reduced code that gives a consumption equivalent to CoreMark code Typical and maximum current consumption The MCU is placed under the following conditions All I O pins are in analog input mode All peripherals are disabled except when explicitly mentioned The Flash memory access time is adjusted to the fHCLK frequency 0 wait state and Prefetch OFF from 0 to 24 MHz 1 wait state and Prefet...

Page 46: ... 3 7 6 7 6 24 MHz 8 9 10 0 10 1 10 2 5 1 5 5 5 8 5 9 HSE bypass PLL off 8 MHz 2 8 3 1 3 3 3 4 1 7 2 0 2 1 2 1 1 MHz 0 3 0 6 0 6 1 3 0 2 0 5 0 8 0 9 HSI clock PLL on 48 MHz 17 4 19 7 20 0 20 2 10 4 11 2 11 3 11 8 32 MHz 11 8 12 8 13 1 13 3 6 8 7 4 7 7 7 9 24 MHz 9 0 10 0 10 1 10 2 5 2 5 7 6 0 6 0 HSI clock PLL off 8 MHz 3 0 3 2 3 5 3 6 1 8 2 0 2 2 2 2 IDD Supply current in Sleep mode code executing...

Page 47: ...3 3 3 5 3 8 4 1 4 4 HSI clock PLL on 48 MHz 220 240 248 252 244 263 275 278 32 MHz 174 191 196 198 193 209 215 218 24 MHz 152 167 173 174 168 183 190 192 HSI clock PLL off 8 MHz 72 79 82 83 83 5 91 94 95 1 Current consumption from the VDDA supply is independent of whether the digital peripherals are enabled or disabled being in Run or Sleep mode or executing from Flash or RAM Furthermore when the ...

Page 48: ... 1 85 2 2 15 2 3 2 45 2 6 3 5 2 3 5 4 5 2 Regulator in low power mode all oscillators OFF 1 85 2 2 15 2 3 2 45 2 6 3 5 2 3 5 4 5 2 Supply current in Standby mode LSI ON and IWDG ON 2 25 2 5 2 65 2 85 3 05 3 3 LSI OFF and IWDG OFF 1 75 1 9 2 2 15 2 3 2 5 3 5 2 3 5 4 5 2 Supply current in Stop mode V DDA monitoring OFF Regulator in run mode all oscillators OFF 1 11 1 15 1 18 1 22 1 27 1 35 Regulator...

Page 49: ...A 25 C TA 85 C TA 105 C IDD_VBAT RTC domain supply current LSE RTC ON Xtal mode lower driving capability LSEDRV 1 0 00 0 47 0 49 0 59 0 65 0 80 0 91 1 0 1 3 1 7 µA LSE RTC ON Xtal mode higher driving capability LSEDRV 1 0 11 0 76 0 79 0 88 0 98 1 13 1 21 1 3 1 6 2 1 1 Data based on characterization results not tested in production 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 微可Vicor 值得信赖的元器...

Page 50: ...y Table 27 Typical current consumption code executing from Flash running from HSE 8 MHz crystal Symbol Parameter fHCLK Typical run mode Typical Sleep mode unit Peripheral s enabled Peripheral s disabled Peripheral s enabled Peripheral s disabled IDD Current from VDD supply 48MHz 20 2 12 3 11 1 2 9 mA 36 MHz 15 3 9 5 8 4 2 4 32 MHz 13 6 8 6 7 5 2 2 24 MHz 10 5 6 7 5 9 1 8 16 MHz 7 2 4 7 4 1 1 4 8 M...

Page 51: ...ting input pin can also settle to an intermediate voltage level or switch inadvertently as a result of external electromagnetic noise To avoid current consumption related to floating pins they must either be configured in analog mode or forced internally to a definite digital value This can be done either by using pull up down resistors or by configuring the pins in output mode I O dynamic current...

Page 52: ...0 37 16 MHz 0 76 24 MHz 1 39 48 MHz 2 188 VDDIOx 3 3 V CEXT 10 pF C CINT CEXT CS 4 MHz 0 32 8 MHz 0 64 16 MHz 1 25 24 MHz 2 23 48 MHz 4 442 VDDIOx 3 3 V CEXT 22 pF C CINT CEXT CS 4 MHz 0 49 8 MHz 0 94 16 MHz 2 38 24 MHz 3 99 VDDIOx 3 3 V CEXT 33 pF C CINT CEXT CS 4 MHz 0 64 8 MHz 1 25 16 MHz 3 24 24 MHz 5 02 VDDIOx 3 3 V CEXT 47 pF C CINT CEXT CS C Cint 4 MHz 0 81 8 MHz 1 7 16 MHz 3 67 VDDIOx 2 4 ...

Page 53: ... on Ambient operating temperature and supply voltage conditions summarized in Table 15 Voltage characteristics The power consumption of the digital part of the on chip peripherals is given in Table 29 The power consumption of the analog part of the peripherals where applicable is indicated in each related section of the datasheet Table 29 Peripheral current consumption Peripheral Typical consumpti...

Page 54: ...tically is active when at least one master is ON CPU or DMA1 2 The APBx Bridge is automatically active when at least one peripheral is ON on the same Bus 3 The power consumption of the analog part IDDA of peripherals such as ADC is not included Refer to the tables of characteristics in the subsequent sections Table 29 Peripheral current consumption continued Peripheral Typical consumption at 25 C ...

Page 55: ...e SYSCLK takes the default setting HSI 8 MHz The wakeup source from Sleep and Stop mode is an EXTI line configured in event mode The wakeup source from Standby mode is the WKUP1 pin PA0 All timings are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 18 General operating conditions Table 30 Low power mode wakeup timings Symbol Parameter C...

Page 56: ...nal clock source AC timing diagram Figure 14 High speed external clock source AC timing diagram Table 31 High speed external user clock characteristics Symbol Parameter 1 1 Guaranteed by design not tested in production Min Typ Max Unit fHSE_ext User external clock source frequency 8 32 MHz VHSEH OSC_IN input pin high level voltage 0 7 VDDIOx VDDIOx V VHSEL OSC_IN input pin low level voltage VSS 0 ...

Page 57: ...d external clock source AC timing diagram Table 32 Low speed external user clock characteristics Symbol Parameter 1 1 Guaranteed by design not tested in production Min Typ Max Unit fLSE_ext User external clock source frequency 32 768 1000 kHz VLSEH OSC32_IN input pin high level voltage 0 7 VDDIOx VDDIOx V VLSEL OSC32_IN input pin low level voltage VSS 0 3 VDDIOx tw LSEH tw LSEL OSC32_IN high or lo...

Page 58: ...st be included 10 pF can be used as a rough estimate of the combined pin and board capacitance when sizing CL1 and CL2 Note For information on selecting the crystal refer to the application note AN2867 Oscillator design guide for ST microcontrollers available from the ST website www st com Table 33 HSE oscillator characteristics Symbol Parameter Conditions 1 1 Resonator characteristics given by th...

Page 59: ...ical application with an 8 MHz crystal 1 REXT value depends on the crystal characteristics 06 9 26 B 1 26 B287 5 LDV FRQWUROOHG JDLQ I 6 5 7 0 UHVRQDWRU 5HVRQDWRU ZLWK LQWHJUDWHG FDSDFLWRUV 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 ...

Page 60: ...racteristics fLSE 32 768 kHz Symbol Parameter Conditions 1 Min 2 Typ Max 2 Unit IDD LSE current consumption LSEDRV 1 0 00 lower driving capability 0 5 0 9 µA LSEDRV 1 0 01 medium low driving capability 1 LSEDRV 1 0 10 medium high driving capability 1 3 LSEDRV 1 0 11 higher driving capability 1 6 gm Oscillator transconductance LSEDRV 1 0 00 lower driving capability 5 µA V LSEDRV 1 0 01 medium low d...

Page 61: ...8 kHz crystal Note An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one 06 9 26 B 1 26 B287 ULYH SURJUDPPDEOH DPSOLILHU I 6 N UHVRQDWRU 5HVRQDWRU ZLWK LQWHJUDWHG FDSDFLWRUV 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 ...

Page 62: ...1 1 VDDA 3 3 V TA 40 to 105 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit fHSI Frequency 8 MHz TRIM HSI user trimming step 1 2 2 Guaranteed by design not tested in production DuCy HSI Duty cycle 45 2 55 2 ACCHSI Accuracy of the HSI oscillator TA 40 to 105 C 2 8 3 3 Data based on characterization results not tested in production 3 8 3 TA 10 to 85 C 1 9 3 2 3 3 TA 0 to 85...

Page 63: ...ncy 14 MHz TRIM HSI14 user trimming step 1 2 2 Guaranteed by design not tested in production DuCy HSI14 Duty cycle 45 2 55 2 ACCHSI14 Accuracy of the HSI14 oscillator factory calibrated TA 40 to 105 C 4 2 3 3 Data based on characterization results not tested in production 5 1 3 TA 10 to 85 C 3 2 3 3 1 3 TA 0 to 70 C 2 5 3 2 3 3 TA 25 C 1 1 tsu HSI14 HSI14 oscillator startup time 1 2 2 2 µs IDDA HS...

Page 64: ...uaranteed by design not tested in production LSI oscillator startup time 85 µs IDDA LSI 2 LSI oscillator power consumption 0 75 1 2 µA Table 38 PLL characteristics Symbol Parameter Value Unit Min Typ Max fPLL_IN PLL input clock 1 1 Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the range defined by fPLL_OUT 1 2 8 0 24 2 MHz PLL input clock duty...

Page 65: ...nctional disturbance occurs This test is compliant with the IEC 61000 4 4 standard A device reset allows normal operations to be resumed The test results are given in Table 41 They are based on the EMS levels and classes defined in application note AN1709 Table 39 Flash memory characteristics Symbol Parameter Conditions Min Typ Max 1 1 Guaranteed by design not tested in production Unit tprog 16 bi...

Page 66: ...range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see application note AN1015 Electromagnetic Interference EMI The electromagnetic field emitted by the device are monitored while a simple application is executed toggling 2 LEDs through the I O ports This emission test is compliant with IEC 61967 2 standard whic...

Page 67: ... 78A IC latch up standard 6 3 13 I O current injection characteristics As a general rule current injection to the I O pins due to external voltage below VSS or above VDDIOx for standard 3 3 V capable I O pins should be avoided during normal product operation However in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens suscept...

Page 68: ... 3 14 I O port characteristics General input output characteristics Unless otherwise specified the parameters given in Table 46 are derived from tests performed under the conditions summarized in Table 18 General operating conditions All I Os are designed as CMOS and TTL compliant except BOOT0 Table 45 I O current injection susceptibility Symbol Description Functional susceptibility Unit Negative ...

Page 69: ...ce 5 pF 1 Data based on design simulation only Not tested in production 2 The leakage could be higher than the maximum value if negative current is injected on adjacent pins Refer to Table 45 I O current injection susceptibility 3 To sustain a voltage higher than VDDIOx 0 3 V the internal pull up pull down resistors must be disabled 4 Pull up and pull down resistors are designed with a true resist...

Page 70: ...or standard I Os and in Figure 21 for 5 V tolerant I Os The following curves are design simulation results not tested in production Figure 20 TC and TTa I O input characteristics MS32130V3 0 0 5 1 1 5 2 2 5 3 1 6 1 8 2 2 2 2 4 2 6 2 8 3 3 2 3 4 3 6 TTL standard requirement TTL standard requirement TTL standard requirement TESTED RANGE TESTED RANGE UNDEFINED INPUT RANGE VDDIOx V VIN V 微可Vicor 值得信赖的...

Page 71: ...Tf I O input characteristics 0 0 5 1 1 5 2 2 5 3 1 6 1 8 2 2 2 2 4 2 6 2 8 3 3 2 3 4 3 6 TTL standard requirement TTL standard requirement TTL standard requirement TESTED RANGE TESTED RANGE VIN V VDDIOx V MS32131V3 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 ...

Page 72: ...ise specified Table 47 Output voltage characteristics 1 Symbol Parameter Conditions Min Max Unit VOL Output low level voltage for an I O pin CMOS port 2 IIO 8 mA VDDIOx 2 7 V 0 4 V VOH Output high level voltage for an I O pin VDDIOx 0 4 VOL Output low level voltage for an I O pin TTL port 2 IIO 8 mA VDDIOx 2 7 V 0 4 V VOH Output high level voltage for an I O pin 2 4 VOL 3 Output low level voltage ...

Page 73: ...Figure 22 CL 50 pF 2 MHz tf IO out Output fall time 125 ns tr IO out Output rise time 125 01 fmax IO out Maximum frequency 3 CL 50 pF 10 MHz tf IO out Output fall time 25 ns tr IO out Output rise time 25 11 fmax IO out Maximum frequency 3 CL 30 pF VDDIOx 2 7 V 50 MHz CL 50 pF VDDIOx 2 7 V 30 CL 50 pF VDDIOx 2 7 V 20 tf IO out Output fall time CL 30 pF VDDIOx 2 7 V 5 ns CL 50 pF VDDIOx 2 7 V 8 CL 5...

Page 74: ...H LV Table 49 NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit VIL NRST NRST input low level voltage 0 3 VDD 0 07 1 V VIH NRST NRST input high level voltage 0 445 VDD 0 398 1 Vhys NRST NRST Schmitt trigger voltage hysteresis 200 mV RPU Weak pull up equivalent resistor 2 VIN VSS 25 40 55 k VF NRST NRST input filtered pulse 100 1 ns VNF NRST NRST input not filtered pulse 2 7 VDD...

Page 75: ...le 18 General operating conditions Note It is recommended to perform a calibration after each power up 538 9 QWHUQDO UHVHW WHUQDO UHVHW FLUFXLW 1567 LOWHU 06 9 Table 50 ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage for ADC ON 2 4 3 6 V IDDA ADC Current consumption of the ADC 1 VDD VDDA 3 3 V 0 9 mA fADC ADC clock frequency 0 6 14 MHz fS 2 Sampling rate...

Page 76: ...trigger conversion fADC fHSI14 1 1 fHSI14 tS 2 Sampling time fADC 14 MHz 0 107 17 1 µs 1 5 239 5 1 fADC tSTAB 2 Power up time 1 Conver sion cycle tCONV 2 Total conversion time including sampling time fADC 14 MHz 1 18 µs 14 to 252 tS for sampling 12 5 for successive approximation 1 fADC 1 During conversion of the sampled value 12 5 x ADC clock period an additional consumption of 100 µA on IDDA and ...

Page 77: ...14 MHz RAIN 10 k VDDA 2 4 V to 3 6 V TA 25 C 3 3 4 LSB EO Offset error 1 9 2 8 EG Gain error 2 8 3 ED Differential linearity error 0 7 1 3 EL Integral linearity error 1 2 1 7 1 ADC DC accuracy values are measured after internal calibration 2 ADC Accuracy vs Negative Injection Current Injecting negative current on any of the standard non robust analog input pins should be avoided as this significan...

Page 78: ...r should be ceramic good quality and it should be placed as close as possible to the chip 7 7RWDO 8QDMXVWHG UURU PD LPXP GHYLDWLRQ EHWZHHQ WKH DFWXDO DQG LGHDO WUDQVIHU FXUYHV 2 2IIVHW UURU PD LPXP GHYLDWLRQ EHWZHHQ WKH ILUVW DFWXDO WUDQVLWLRQ DQG WKH ILUVW LGHDO RQH DLQ UURU GHYLDWLRQ EHWZHHQ WKH ODVW LGHDO WUDQVLWLRQ DQG WKH ODVW DFWXDO RQH LIIHUHQWLDO LQHDULW UURU PD LPXP GHYLDWLRQ EHWZHHQ DFWX...

Page 79: ...1 Guaranteed by design not tested in production 2 Measured at VDDA 3 3 V 10 mV The V30 ADC conversion result is stored in the TS_CAL1 byte Refer to Table 3 Temperature sensor calibration values Table 54 VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT 2 x 50 k Q Ratio on VBAT measurement 2 Er 1 Error on Q 1 1 tS_vbat 1 ADC sampling time when reading the ...

Page 80: ...or the I2C I Os characteristics tMAX_COUNT Maximum possible count with 32 bit counter 65536 65536 tTIMxCLK fTIMxCLK 48 MHz 89 48 s Table 56 IWDG min max timeout period at 40 kHz LSI 1 1 These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30 to 60 kHz Moreover given an exact RC oscillator frequency the exact timings still depend on the phasing of t...

Page 81: ... analog filter characteristics 1 1 Guaranteed by design not tested in production Symbol Parameter Min Max Unit tAF Maximum pulse width of spikes that are suppressed by the analog filter 50 2 2 Spikes with widths below tAF min are filtered 260 3 3 Spikes with widths above tAF max are not filtered ns 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660...

Page 82: ... SCKH tw SCKL SCK high and low time Master mode fPCLK 36 MHz presc 4 Tpclk 2 2 Tpclk 2 1 tsu MI tsu SI Data input setup time Master mode 4 Slave mode 5 th MI Data input hold time Master mode 4 th SI Slave mode 5 ta SO 2 Data output access time Slave mode fPCLK 20 MHz 0 3Tpclk tdis SO 3 Data output disable time Slave mode 0 18 tv SO Data output valid time Slave mode after enable edge 22 5 tv MO Dat...

Page 83: ...d 0 7 VDD DL F 6 QSXW 166 LQSXW W68 166 WF 6 WK 166 3 32 3 32 WZ 6 WZ 6 W9 62 WK 62 WU 6 WI 6 WGLV 62 WD 62 0 62 287387 026 1387 06 287 7 287 6 287 WVX 6 WK 6 06 1 7 1 6 1 DL E 166 LQSXW W68 166 WF 6 WK 166 6 LQSXW 3 32 3 32 WZ 6 WZ 6 WD 62 WY 62 WK 62 WU 6 WI 6 WGLV 62 0 62 287387 026 1387 WVX 6 WK 6 06 287 06 1 7 287 6 287 6 1 7 1 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 微可Vicor 值得信赖的...

Page 84: ...x Unit fCK 1 tc CK I2 S clock frequency Master mode data 16 bits Audio frequency 48 kHz 1 597 1 601 MHz Slave mode 0 6 5 tr CK I2 S clock rise time Capacitive load CL 15 pF 10 ns tf CK I2S clock fall time 12 tw CKH I2S clock high time Master fPCLK 16 MHz audio frequency 48 kHz 306 tw CKL I2S clock low time 312 tv WS WS valid time Master mode 2 th WS WS hold time Master mode 2 tsu WS WS setup time ...

Page 85: ...edge Slave transmitter after enable edge Master transmitter after enable edge Master transmitter after enable edge 20 th SD_ST Data output hold time 13 tv SD_MT 2 Data output valid time 4 th SD_MT Data output hold time 0 1 Data based on design simulation and or characterization results not tested in production 2 Depends on fPCLK For example if fPCLK 8 MHz then TPCLK 1 fPLCLK 125 ns Table 60 I2 S c...

Page 86: ... transmit receive of the previously transmitted byte No LSB transmit receive is sent before the first byte OUTPUT 0 0 TC 73 OUTPUT 3 RECEIVE 3 TRANSMIT TW TW TSU 3 2 TV 3 4 TH 3 4 TH 73 TH 3 2 3 RECEIVE ITN RECEIVE 3 RECEIVE 3 TRANSMIT ITN TRANSMIT 3 TRANSMIT AI B TF TR TV 73 3 RECEIVE 3 TRANSMIT 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 3166049...

Page 87: ...their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark 7 1 LQFP48 package information Figure 31 LQFP48 48 pin 7 x 7 mm low profile quad flat package outline 1 Drawing is not to scale 6 0 4 4 CCC MM 5 0 B C E 3 4 0 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 微可Vicor 值得信赖的元器件供应商 http www vicor...

Page 88: ...2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 c 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 500 0 2165 E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 500 0 2165 e 0 500 0 0197 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 3 5 7 0 3 5 7 cc...

Page 89: ...age information 109 Figure 32 LQFP48 48 pin 7 x 7 mm low profile quad flat package recommended footprint 1 Dimensions are expressed in millimeters AI D 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 ...

Page 90: ...ified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity 06 9 3URGXFW LGHQWLILFDWLRQ 3LQ LGHQWLILHU 5HYLVLRQ FRGH D...

Page 91: ... 109 7 2 LQFP32 package information Figure 34 LQFP32 32 pin 7 x 7 mm low profile quad flat package outline 1 Drawing is not to scale C B 5 0 MM 3 4 0 0 4 4 CCC 7 7 E 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 ...

Page 92: ...2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 300 0 370 0 450 0 0118 0 0146 0 0177 c 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 600 0 2205 E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 600 0 2205 e 0 800 0 0315 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 3 5 7 0 3 5 7 cc...

Page 93: ...d by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification acti...

Page 94: ... package information Figure 37 UFQFPN32 32 pin 5x5 mm 0 5 mm pitch ultra thin fine pitch quad flat package outline 1 Drawing is not to scale 6 3 1 GHQWLILHU 6 7 1 3 1 GGG H E E H 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 ...

Page 95: ...decimal digits Min Typ Max Min Typ Max A 0 500 0 550 0 600 0 0197 0 0217 0 0236 A1 0 000 0 020 0 050 0 0000 0 0008 0 0020 A3 0 152 0 0060 b 0 180 0 230 0 280 0 0071 0 0091 0 0110 D 4 900 5 000 5 100 0 1929 0 1969 0 2008 D1 3 400 3 500 3 600 0 1339 0 1378 0 1417 D2 3 400 3 500 3 600 0 1339 0 1378 0 1417 E 4 900 5 000 5 100 0 1929 0 1969 0 2008 E1 3 400 3 500 3 600 0 1339 0 1378 0 1417 E2 3 400 3 50...

Page 96: ...qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity 3URGXFW LGHQWLILFDWLRQ 3LQ LGHQWLILHU 5HYLVLRQ FRGH DW...

Page 97: ...meters inches Min Typ Max Min Typ Max A 0 500 0 550 0 600 0 0197 0 0217 0 0236 A1 0 000 0 050 0 0000 0 0020 D 3 900 4 000 4 100 0 1535 0 1575 0 1614 D1 2 900 3 000 3 100 0 1142 0 1181 0 1220 E 3 900 4 000 4 100 0 1535 0 1575 0 1614 E1 2 900 3 000 3 100 0 1142 0 1181 0 1220 L 0 300 0 400 0 500 0 0118 0 0157 0 0197 L1 0 250 0 350 0 450 0 0098 0 0138 0 0177 T 0 152 0 0060 b 0 200 0 250 0 300 0 0079 0...

Page 98: ... mm 0 5 mm pitch ultra thin fine pitch quad flat package recommended footprint 1 Dimensions are expressed in millimeters 1 Values in inches are converted from mm and rounded to 4 decimal digits 0 6 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 ...

Page 99: ... not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity 06 9 3URGXFW LGHQWLILFDWLRQ RW 5HYLVLRQ FRGH ...

Page 100: ...ymbol millimeters inches 1 Min Typ Max Min Typ Max A 0 525 0 555 0 585 0 0207 0 0219 0 0230 A1 0 175 0 0069 A2 0 380 0 0150 A3 2 0 025 0 0010 b 3 4 0 220 0 250 0 280 0 0087 0 0098 0 0110 D 2 388 2 423 2 458 0 0940 0 0954 0 0968 E 2 29 2 325 2 36 0 0902 0 0915 0 0929 e 0 400 0 0157 e1 1 600 0 0630 63 B 1B0 B9 RULHQWDWLRQ UHIHUHQFH DIHU EDFN VLGH HWDLO URWDWHG 6HDWLQJ SODQH XPS E 6LGH YLHZ HWDLO H H...

Page 101: ...m bump diameter parallel to primary datum Z 4 Primary datum Z and seating plane are defined by the spherical crowns of the bump Table 66 WLCSP25 recommended PCB design rules 0 4 mm pitch Dimension Recommended values Pitch 0 4 mm Dpad 0 225 mm Dsm 0 290 mm typ depends on the soldermask registration tolerance Stencil opening 0 250 mm Stencil thickness 0 100 mm Table 65 WLCSP25 25 ball 2 423 x 2 325 ...

Page 102: ...r are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity 06 9 5HYLVLRQ FRGH 88 3 DWH FRGH 3URGXFW...

Page 103: ...Symbol millimeters inches 1 Min Typ Max Min Typ Max A 1 200 0 0472 A1 0 050 0 150 0 0020 0 0059 A2 0 800 1 000 1 050 0 0315 0 0394 0 0413 b 0 190 0 300 0 0075 0 0118 c 0 090 0 200 0 0035 0 0079 D 2 6 400 6 500 6 600 0 2520 0 2559 0 2598 E 6 200 6 400 6 600 0 2441 0 2520 0 2598 E1 3 4 300 4 400 4 500 0 1693 0 1732 0 1772 e 0 650 0 0256 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 9 6 C ...

Page 104: ...D does not include mold flash protrusions or gate burrs Mold flash protrusions or gate burrs shall not exceed 0 15mm per side 3 Dimension E1 does not include interlead flash or protrusions Interlead flash or protrusions shall not exceed 0 25mm per side Table 67 TSSOP20 20 lead thin shrink small outline 6 5 x 4 4 mm 0 65 mm pitch package mechanical data continued Symbol millimeters inches 1 Min Typ...

Page 105: ... qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity 3URGXFW LGHQWLILFDWLRQ 3LQ LGHQWLILHU 5HYLVLRQ FRGH D...

Page 106: ...ents the maximum power dissipation on output pins where PI O max VOL IOL VDDIOx VOH IOH taking into account the actual VOL IOL and VOH IOH of the I Os at low and high level in the application 7 8 1 Reference document JESD51 2 Integrated Circuits Thermal Test Method Environment Conditions Natural Convection Still Air Available from www jedec org Table 68 Package thermal characteristics Symbol Param...

Page 107: ... low level with IOL 8 mA VOL 0 4 V and maximum 8 I Os used at the same time in output at low level with IOL 20 mA VOL 1 3 V PINTmax 50 mA 3 5 V 175 mW PIOmax 20 8 mA 0 4 V 8 20 mA 1 3 V 272 mW This gives PINTmax 175 mW and PIOmax 272 mW PDmax 175 272 447 mW Using the values obtained in Table 68 TJmax is calculated as follows For LQFP48 55 C W TJmax 80 C 55 C W 447 mW 80 C 24 585 C 104 585 C This i...

Page 108: ...INTmax 70 mW and PIOmax 64 mW PDmax 70 64 134 mW Thus PDmax 134 mW Using the values obtained in Table 68 TJmax is calculated as follows For LQFP48 55 C W TJmax 100 C 55 C W 134 mW 100 C 7 37 C 107 37 C This is above the range of the suffix 6 version parts 40 TJ 105 C In this case parts must be ordered at least with the temperature range suffix 7 see Section 8 Part numbering unless we reduce the po...

Page 109: ...2 F 031 G 6 T 6 x Device family STM32 ARM based 32 bit microcontroller Product type F General purpose Sub family 031 STM32F031xx Pin count F 20 pins E 25 pins G 28 pins K 32 pins C 48 pins Code size 4 16 Kbytes of Flash memory 6 32 Kbytes of Flash memory Package P TSSOP U UFQFPN T LQFP Y WLCSP Temperature range 6 40 C to 85 C 7 40 C to 105 C Options xxx programmed parts TR tape and reel 微可Vicor 值得...

Page 110: ...1x6 110 113 DocID025743 Rev 3 9 Revision history Table 70 Document revision history Date Revision Changes 13 Jan 2014 1 Initial release 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 微可Vicor 值得信赖的元器件供应商 http www vicor top 021 31660491 ...

Page 111: ... consumption in Run mode code with data processing running from Flash and Table Typical current consumption in Sleep mode code running from Flash or RAM with Table Typical current consumption code executing from Flash running from HSE 8 MHz crystal Added the LQFP32 package updates in Section Description Section Pinouts and pin description and Section Package information Table 70 Document revision ...

Page 112: ...nformation Added Figure 33 LQFP48 marking example package top view Figure 36 LQFP32 marking example package top view Figure 39 UFQFPN32 marking example package top view Figure 42 UFQFPN28 marking example package top view Figure 48 TSSOP20 marking example package top view Added WLCSP25 package updates in the following Table 1 Device summary Section 2 Description Table 2 STM32F031x4 x6 family device...

Page 113: ...ice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to any intellectual property right is granted by ST herein Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product ST and the ST logo are trademarks of ST A...

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