RM0082
RS_Telecom IP
Doc ID 018672 Rev 1
799/844
RESET: all ‘0’
Table 721.
I2S_CONF register (Offset 0x4C)
Bits
Name
Comments
[31]
I2S_IT
When I2S_IT =1, an I2S interrupt is in progress (after bank
switching)
[30:28]
Reserved
[27]
BANK
Read only bit. Indicates the I2S memory bank being accessed
by the I2S block to allow the processor to be synchronized with
the samples memory.
[26]
FRC_BK
Force bank.
When FRC_BK = 0,
the processor will access the two memory
banks using address12-0.
When FRC_BK =1
, the processor will access only the memory
bank containing the samples of the previous buffer. Only
processor address bits 11 to 0 are taken into account. Bit 12 is
inserted by the I2S state machine.
[25:24]
DTo
Output transfer size. The goal is to left align the data received
from the 32 bit transmit memory if necessary. According to the
data size, the not used bits are filled with zero.
DTo1-DTo0
Transfer
Output Data
00
8->32
8 bits
01
16->32
16 bits
10
24->32
24 bits
11
32->32
32 bits
[23]
invint
inversion of TDM internal sync when selected by intsel
when invint = 0,
no action
when invint = 1,
if TDM internal sync is selected by Intsel, it will
be inverted before being used by the I2S block.
[22]
instel
select the TDM internal sync signal instead of the I2S
generated one
when intsel =0,
the generated I2S sync signal is used to the I2S
block
when intsel = 1
,
the TDM internal sync signal is used instead
the locally generated.
[21:12]
NS
Number of samples to recover before switching bank.
[11:10]
DTi
Input transfer size. The goal is to left align the data in the 32 bit
receive memory if necessary (from din pin to memory).
According to the data size, the not used bits are filled with zero.
DTi1-DTi0
Transfer
Input Data
00
8->32
8 bits
01
16->32
16 bits
10
24->32
24 bits
11
32->32
32 bits
