RM0082
RS_Color liquid crystal display controller (CLCD)
Doc ID 018672 Rev 1
741/844
The inherent AMBA AHB master interface state machine performs the following functions:
●
Loads the upper panel base address into the AMBA AHB address incrementor on
recognition of a new frame.
●
Monitors both the upper and lower DMA FIFO levels and asserts HBUSREQM to
request display data from memory, filling them to above the programmed water mark.
HBUSREQM is re-asserted when there are at least four locations available within either
FIFO (dual panel mode).
●
Checks for 1KB boundaries during fixed-length bursts and appropriately adjusts the
address in such occurrences.
●
Generates the address sequences for fixed-length and undefined bursts.
●
Controls the handshaking between the memory and DMA FIFOs. It inserts busy cycles
if the FIFOs have not completed their synchronization and updating sequence.
●
Fills up the DMA FIFOs, in dual panel mode, in an alternating fashion from a single
HBUSREQM request and subsequent HGRANTM.
●
Asserts the CLCDMBEINTR interrupt if an error occurs during an active burst.
●
Responds to retry commands by restarting the failed access.
33.5.3
Dual DMA FIFOs and associated control logic
The pixel data accessed from memory is buffered by two DMA FIFOs that can be
independently controlled to cover single and dual-panel LCD types. Each FIFO is 16 words
deep by 32 bits wide and can be cascaded to form an effective 32-word deep FIFO in single-
panel mode. The input ports of the FIFOs are connected to the AMBA AHB interface and the
output port feeds the pixel serializer.
Synchronization logic is used to transfer the pixel data from the AMBA AHB
HCLK
domain to
the CLCDCLK clock domain, the DMA FIFOs being clocked by the former.
The water level marks within each FIFO are set so that each FIFO requests data when at
least four locations become available.
An interrupt signal is asserted if an attempt is made to read either of the two DMA FIFOs
when they are empty, in other words an underflow condition has occurred.
33.5.4 Pixel
serializer
This block reads the 32 bit wide LCD data from output port of the DMA FIFO and extracts
24, 16, 8, 4, 2, or 1 bpp data, depending on the current mode of operation. The CLCD
supports big-endian, little-endian, and WinCE data formats. In dual panel mode, data is
alternately read from the upper and lower DMA FIFOs. Depending upon the mode of
operation, you can use the extracted data to point to a color/gray scale value in the palette
RAM or it can be a true color value that you can apply directly to an LCD panel input.
The following tables shows the structure of the data in each DMA FIFO word corresponding
to the endianness and bpp combinations. For each of the three supported data formats, the
required data for each panel display pixel must be extracted from the data word.
The nomenclature used in the figures is:
●
Little endian byte, little endian pixel (LBLP) order (
and
●
Big endian byte, big endian pixel (BBBP) order (
and
●
Little endian byte, big endian pixel (LBBP) order (this is the WinCE format) (
Powering
up and down sequences
and
)
