RM0082
RS_SDIO controller
Doc ID 018672 Rev 1
683/844
32.5 Functional
overview
This section describes the functional overview of SDIO.
Figure 69.
Architectural block diagram
The AHB interface acts as the bridge between AHB and Host Controller. The SD/SDIO
controller registers are programmed by the ARM Processor through AHB target interface.
Interrupts are generated to the ARM Processor based on the values set in the Interrupt
status register and Interrupt enable registers. The Clock generation block will generate the
SD clock depending on the value programmed by the ARM Processor in the Clock Control
Register. The CRC7 and CRC16 generators calculate the CRC for command and Data
respectively to send the CRC to the SD card. The CRC7 and CRC16 checker checks for any
CRC error in the Response and Data sent by the SD/SDIO card.
The host controller alternatively uses two dual port 4KB FIFOs for read (data transferred
from card to processor) and write (data transferred from processor to card) transactions.
The DAT[0-7] control logic block transmits data in the data lines during write transaction and
receives data in the data lines during read transaction.
The Command control logic block sends the command in the CMD line and receives the
response coming from the SD2.0/SDIO2.0/MMC4.2 card.
DB_RAM2[31:0]
OUT
Data in for PORT B FIFO 2
CENB_RAM2
OUT
Chip enable for PORT B FIFO 2
WENB_RAM2
OUT
Write enable for PORT B FIFO 2
QA_RAM1[31:0]
IN
DATA OUT From PORT A FIFO 1
QB_RAM1[31:0]
IN
DATA OUT From PORT B FIFO 1
QA_RAM2[31:0]
IN
DATA OUT From PORT A FIFO 2
QB_RAM2[31:0]
IN
DATA OUT From PORT B FIFO 2
Table 614.
RAM Interface signals (continued)
Signal
DIR
Description
Power
Management
AHB
Interface
SD
Registers
Data
FIFO
Synch
ronizer
Bus Monitor
Clock
Control
SD Protocol
Unit
Command
Control
Unit
Data
Control
Unit
SDIO2.0/
SDIO2.0 Mem
MMC 3.31/4.2
AHB
B
U
S
