RS_Flexible static memory controller (FSMC)
RM0082
662/844
Doc ID 018672 Rev 1
31
RS_Flexible static memory controller (FSMC)
31.1 Overview
Within its Reconfigurable Array Subsystem, SPEAr300 provides a Flexible Static Memory
Controller (FSMC) which is intended to interface an AHB bus to external NAND/NOR Flash
memories and to asynchronous SRAM memories.
The controller:
●
Translates AHB protocol into the appropriate external storage device protocol,
●
Meets the timing of the external devices, slowing down and counting an appropriate
number of HCLK (AHB clock) cycles to complete the transaction to the external device.
Note:
The external storage device cannot be faster than one AHB cycle.
Main features of FSMC:
●
AHB slave interface
●
Interfaces static memory-mapped devices including RAM and Flash (both NAND and
NOR).
●
In case of Swims and Flash 8 and 16 bit wide, it provides external address and data
paths;
●
Performs only one access at a time;
●
Supplies an independent configuration for each memory bank;
●
Provides programmable timings to support a wide range of devices:
●
programmable wait states (up to 31),
●
programmable bus turn around cycles (up to 15),
●
programmable output enable and write enable delays (up to 15).
●
Provides independent chip select control for each memory bank;
●
The address bus and the data bus are shared with all the external peripherals,
●
Chip selects used to distinguish between each peripheral;
●
Offers an external asynchronous wait control;
●
Offers configurable size at reset for boot memory bank using RAS configuration
registers.
