RM0082
LS_I2C controller
Doc ID 018672 Rev 1
607/844
28 LS_I2C
controller
This chapter describes the I2C Controller which is part of the low speed connectivity
subsystem of the SPEAr
TM
device. SPEAr300 has two I2C interfaces - one in fixed logic and
another in the RAS subsystem.
28.1 Overview
The I2C Controller provides an APB interface to the processor to access the two-wire serial
I2C bus. It can be used to connect any device which conforms to the I2C-Bus Specification
from Philips.’
Main features of the I
2
C controller are:
●
Compliance to the I
2
C-bus specification from Phillips.
●
Operates in three different modes:
–
Standard-speed mode (data rates up to 100 Kb/s)
–
Fast-speed mode (data rates up to 400 Kb/s)
–
High-speed mode (data rates up to 3.4 Mb/s)
●
Provides clock synchronization.
●
Supports either master (only in a single master environment) or slave I
2
C operation
mode.
●
Supports only slave operation in multi-master environment;
●
Provides 7 bit or 10 bit addressing both in master and slave mode;
●
Supports 7 bit or 10 bit combined format transfers.
●
Provides slave bulk transfer mode.
●
Ignores CBUS addresses (an older ancestor of I
2
C that used to share the I
2
C bus).
●
Transmits and receives buffers.
●
Provides interrupt or polled-mode operation.
●
Handles bit and byte waiting at all bus speeds.
●
Provides digital filter for the received SDA and SCL lines.
●
Provides a DMA handshaking interface compatible with SPEAr
TM
Basic's DMA
Controller handshaking interface (see the Chapter on DMA Controller);
●
Provides 8 or 16 bit wide transaction on the APB bus.
28.2 Block
diagram
shows the functional block diagram of the I
2
C controller.
