STMicroelectronics SPEAr300, Reference Manual

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RM0082 HS_Media independent interface (MII)
Doc ID 018672 Rev 1 509/844
Figure 51. DMA descriptor list: ring structure (left) and chain structure (right).
Note: The descriptor addresses must be aligned to the bus-width used (32/64/128 bit buses).
24.4.1 Transmit descriptors
According to Figure 52. , there are four different Transmit Descriptors:
●
Transmit Descriptor 0, TDES0 ( Table 414 ): it contains the status of the transmitted
frame and the descriptor ownership information along with control bits for controlling
the descriptor structure and the frame being transferred;
● Transmit Descriptor 1, TDES1 ( Table 415 ): it contains the data buffer sizes;
●
Transmit Descriptor 2, TDES2 ( Table 416 ): it contains the address pointer to the first
data buffer in the descriptor;
● Transmit Descriptor 3, TDES3 ( Table 417 ): it contains the address pointer to the
second data buffer in the descriptor or the next descriptor (in case of chained structure)
Buffer 1
Descriptor 0
Descriptor 1
Descriptor 2
Descriptor n
Buffer 2
Buffer 1
Buffer 1
Buffer 1
Buffer 2
Buffer 2
Buffer 2
Buffer 1
Buffer 1
Buffer 1
Descriptor 0
Descriptor 1
Descriptor 2
Next Descriptor