RM0082
DDR memory controller (MPMC)
Doc ID 018672 Rev 1
139/844
Note:
The values in lowpower_auto_enable parameter are only relevant when the associated
lowpower_control bit is set to 1'b1.
Multiple bits of the lowpower_control and lowpower_auto_enable parameters can be set to
1'b1 at the same time. When this happens, the Memory Controller always enters the
deepest low power mode of all the modes that are enabled.
If the Memory Controller is already in one low power mode when a deeper low power mode
is automatically or manually requested, first it exits the current low power mode and then
enters the deeper low power mode. A minimum 15 cycle delay occurs before the second
entry occurs.
The timing for automatic entry into any of the low power modes is based on the number of
idle cycles that have elapsed in the Memory Controller. There are 4 counters related to the 5
low power modes to determine when any particular low power mode will be entered if the
automatic entry option is chosen. The counters are also shown in
. Since the two
power-down modes share one counter, wishing the user automatically enter Memory Power-
Down mode (Mode 1), the Memory Power-Down with Memory Clock Gating mode (Mode 2)
must not be enabled.
Controller clock gating and Re-locking
When the Memory Controller is in its deepest low power modes, the clock to the Memory
Controller is gated off, except a small portion of the DLL to maintain the current frequency.
Since the voltage and temperature differences of the chip can change and the DLL would
not adjust to these changes, it is possible that the Memory Controller DLL shifts out of range
of the controller clock.
The DLL can respond to slight variations of the frequency very quickly, but it requires a long
time to manage large shifts. Therefore, it is better the Memory Controller to be periodically
awoken from controller clock gating, so it can resynchronize to the controller clock and then
resume controller clock gating.
The interval among synchronizations is user-defined by the lowpower_refresh_hold
parameter. This value directly feeds a counter and sets the number of cycles that the
Memory Controller will wait before attempting to re-lock the DLL.
Note:
This is only relevant when the controller clock is gated (Mode 5).
When this counter expires, the DLL will be un-gated and the DLL will attempt to re-lock. The
clock will be kept un-gated for at least 16 cycles, even if the DLL locks during that time. Once
the DLL has re-locked and the 16 cycles have elapsed, the DLL controller clock will be gated
again and the counter will restart countdown at the value in the lowpower_refresh_hold
parameter.
Table 71.
Low power mode controls
Low Power Mode
Counter
Memory Power-Down (Mode 1)
lowpower_power_down_cnt
Memory Power-Down with Memory Clock Gating (Mode 2)
lowpower_power_down_cnt
Memory Self-Refresh (Mode 3)
lowpower_self_refresh_cnt
Memory Self-Refresh with Memory Clock Gating (Mode 4)
lowpower_external_cnt
Memory Self-Refresh with Memory and Controller Clock Gating
(Mode 5)
lowpower_internal_cn
t
