Stanford Research Systems SR860, Operation Manual

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152 Programming Chapter 4
SR860 DSP Lock-in Amplifier
set will generate a single SRQ. If another service request from the same status bit is
desired, the requesting status bit must first be cleared. In the case of the ERR, LIA and
ESB bits, this means clearing the enabled bits in the ERR, LIA and ESB status bytes (by
reading them). Multiple enabled bits in these status bytes will generate a single SRQ.
Another SRQ (from ERR, LIA or ESB) can only be generated after clearing the ERR,
LIA or ESB bits in the Serial Poll status byte. To clear these bits, ALL enabled bits in the
ERR, LIA or ESB status bytes must be cleared.
The controller should respond to the SRQ by performing a serial poll to read the Serial
Poll status byte to determine the requesting status bit. Bit 6 (SRQ) will be reset by the
serial poll.
For example, to generate a service request when a reference UNLK occurs, bit 3 in the
LIA Status Enable register needs to be set (
LIAE 3,1
command) and bit 3 in the Serial
Poll Enable register must be set (
*SRE 3,1
command). When a reference unlock occurs,
bit 3 in the LIA Status byte is set. Since bit 3 in the LIA Status byte AND Enable register
is set, this ALSO sets bit 3 (LIA) in the Serial Poll Status byte. Since bit 3 in the Serial
Poll Status byte AND Enable register is set, an SRQ is generated. Bit 6 (SRQ) in the
Serial Poll Status byte is set. Further reference unlocks will not generate another SRQ
until the UNLK status bit is cleared. The UNLK status bit is cleared by reading the LIA
Status byte (with
LIAS?
). Presumably, the controller is alerted to the unlock via the SRQ,
performs a serial poll to clear the SRQ, does something to try to remedy the situation
(change frequency, experimental parameters, etc.) and then clears the UNLK status bit by
reading the LIA status register. A subsequent UNLK overload will then generate another
SRQ.
Standard Event Status Byte
bit name usage
0 OPC Operation complete (set by the *OPC command)
1 INP Input queue overflow (too many commands received at once, queues
cleared).
2 unused
3 QRY Output queue overflow (too many responses waiting to be
transmitted, queues cleared).
4 EXE A command cannot execute correctly or a parameter is out of range.
5 CMD An illegal command is received.
6 URQ Set by any user front panel action.
7 PON Set by power-on.
The bits in this register remain set until cleared by reading them or by the
*CLS
command.