Stanford Research Systems SR620, Manual

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Circuit Description 81
SR620 Universal Time Interval Counter
Gate_Ctrl sets U506A: the next rising edge of the
frequency source sets U508A high, and the
second rising edge sets U509A, Freq_Start, high.
Freq_Start is selected as the start to the time
interval counter by U502. The -Q of U509A also
asserts Freq_Gate to allow the cycles of the
frequency source to be counted until Freq_Stop is
asserted. The falling edge of the Gate_Ctrl bit sets
U506B. U508B and U509B are used to generate a
Freq_Stop bit which is synchronous with the
second rising edge of the frequency source after
Gate_Ctrl goes low. Freq_Stop is selected as the
stop input to the time interval counter by U503,
and is used to turn off the Freq_Gate bit to stop
the cycle counter for the frequency input.
To measure a single cycle of the input source, -
Int_Arm is asserted so that U506A & B will be
asserted immediately after the LOAD pulse is
removed. The first rising edge of the frequency
source will set U508A and remove the reset to the
U508B. The next rising edge will set U509A, the
Freq_Start bit, and remove the reset from U509B.
The third rising edge will set U509B, the
Freq_Stop bit. The time between Freq_Start and
Freq_Stop is equal to one cycle of the frequency
input source.
To externally gate, the bit Int_Gaten is set low,
allowing the discriminated EXT input (Cmp3) to
pass to the XOR gate, U430C. The Gate_Ctrl bit is
now used to control the polarity of the EXT input
which is to arm the unit. The frequency gate starts
when U506A is set by the rising edge of the non-
inverted output of U430C, and the gate is
terminated by the rising edge of the inverted
output of U430C. (The bit Par_Hoff is high.) The
synchronization of the Freq_Start and Freq_Stop
bit works as described above for internal gating.
Regardless of gate width, at least one cycle of the
input will always be measured.
If -Fast_Per is low, then the first stage of re-
synchronization is skipped, as U506A and U506B
will be set when the Load pulse is terminated
which will cause U508A and U508B to be set. In
this case, the first rising edge of the selected
frequency source will set U509A (the Start) and
the second edge will set U509B (the Stop). This
mode is not used.
EVENT GATING
(Sheet 9 of 16)
There are three modes of generating a gate for
event counting: fixed gates from 1 us to 1 s,
delayed/scanning gates from an external trigger,
and external gating. The event gate is open from
the time U506A is set until U506B is set. The or-
gate, U507C, forms the Event_Gate which
enables the event counters via the multiplexer,
U504.
For internal gates, Int_Gaten is set high and the
gate is controlled by Gate_Ctrl from the 8254
counter/timers on sheet 6 of 16. The counter
timers may provide fixed gates, or gates which
may be delayed or scanned relative to an external
trigger.
For external gates, the Par_Hoff bit is set high,
and the the discriminated output of the EXTernal
input is used to clock U506A and U506B. The
polarity of the external gate is controlled by the
Gate_Ctrl bit.
COUNTING CHANNELS
(Sheet 9 of 16)
There are two gated counting channels capable of
250 MHz operation and a count capacity of 10
16
.
The gate and count inputs to the counters are
selected by the multiplexer U504. The selected
input clocks a D-type flip-flop. This flip-flop will
count if the selected gate is high. (To count, the D-
input must see the inverted output of the flip-flop.
The XOR gate inverts the input to the D input
when the gate is high.) The counter channel
continues with another ECL flip-flop, conversion to
TTL level, and a 74F74 flip-flop. The output of the
74F74 flip-flop is passed to a 74HC191 4-bit
counter (sheet 6 of 16) and on to the counter
inputs of the central processor.
When counting events, the top counter counts the
Start_Mpx output, the bottom counter counts the
Stop_Mpx output, and both counters are gated by
the Event_Gate. In all other modes of operation,
the top counter counts the 90MHz_C ticks and is
gated by the Time_Gate, and the bottom counter
counts the output of the frequency source
multiplexer, U501, (to count cycles in the
frequency mode) and is gated by the Freq_Gate.
The ECL counters are reset by the "Load" pulse,
and the CMOS counters are reset by the "-Reload"
pulse.
Fast transition time TTL outputs which drive long
lines have 82 Ohm series resistors on their
outputs to improve the pulse shape at the end of
the line. A 4 V step at the source will launch a 2 V
wave. The line, which has a characteristic
impedance of about 100 Ohms, will provide a