Development and debugging tool support
AN2339
16/20
5.2.2
Minimizing signal skew (balancing PCB track lengths)
You must attempt to match the lengths of the PCB tracks carrying all of
TRACECLK
,
PIPESTAT
,
TRACESYNC,
and
TRACEPKT
from the STR91x to the Mictor connector to
within approximately 0.5 inches (12.5mm) of each other. Any greater differences directly
impact the setup and hold time requirements.
5.2.3 Minimizing
crosstalk
Normal high-speed design rules must be observed. For example, do not run dynamic
signals parallel to each other for any significant distance, keep them spaced well apart, and
use a ground plane and so forth. Particular attention must be paid to the
TRACECLK
signal.
If in any doubt, place grounds or static signals between the
TRACECLK
and any other
dynamic signals.
5.2.4
Impedance matching and termination
Termination is almost certainly necessary, but there are some circumstances where it is not
required. The decision is related to track length between the STR91x and the Mictor
connector.
5.2.5
Rules for series terminators
Series (source) termination is the most commonly used method. The basic rules are:
Vsupply
V33
14
Supply voltage
Port A TRACEPKT[7]
Not used
16
The trace packet port
Port A TRACEPKT[6]
Not used
18
The trace packet port
Port A TRACEPKT[5]
Not used
20
The trace packet port
Port A TRACEPKT[4]
Not used
22
The trace packet port
Port A TRACEPKT[3]
ETM_PCK3
24
The trace packet port
Port A TRACEPKT[2]
ETM_PCK2
26
The trace packet port
Port A TRACEPKT[1]
ETM_PCK1
28
The trace packet port
Port A TRACEPKT[0]
ETM_PCK0
30
The trace packet port
Port A TRACESYNC
ETM_TRSYNC
32
Start of branch sequence signal
Port A PIPESTAT[2]
ETM_PSTAT2
34
RAM pipeline status
Port A PIPESTAT[1]
ETM_PSTAT2
36
RAM pipeline status
Port A PIPESTAT[0]
ETM_PSTAT1
38
RAM pipeline status
Table 3.
ETM interface signals
Target board
STR91x
name
Signal
pin
Description