ST STR91 Series, Application Note, Page: 10 / 20

Reset control AN2339
10/20
4 Reset control
There are two types of internal hardware reset, defined as System Reset and Global Reset.
The STR91x device also provides a Reset output signal.
4.1 Reset input
4.1.1 System Reset
A system reset resets all registers except the Clock Control Register, PLL Configuration
Register, System Status Register, Flash Configuration register, Protection register and the
FMI Bank address and Bank size Registers.
A system reset is generated when one of the following events occurs:
●
A low level on the RESET_INn pin (External Reset):
– This input signal is active low. It has no internal pull-up to VDDQ. A valid active-low
input signal of t
RINMIN
= 100ns.
●
JTAG Reset Command (JTAG reset):
The JTAG interface has two reset signals connected to the debug target hardware:
– nTRST drives the JTAG nTRST signal on the ARM processor core. It is an open
collector output that is activated whenever the In-Circuit Emulators (ICE) software
has to re-initialize the debug interface in the target system.
– nSRST is a bidirectional signal that both drives and senses the system reset
signal on the target. The open collector output is driven LOW by the debugger to
re-initialize the target system.
●
Watchdog reset
– In Watchdog mode, a reset is generated when the counter reaches the end of
count.
For more details, refer to Section 5.1: JTAG interface on page 12
Note: If the nRESET and nTRST signals are linked together, resetting the system also resets the
TAP controller.
4.1.2 Global Reset
A global reset sets all the registers to their reset values, it is generated when one of the
following events occurs:
LVD circuitry
LVD circuitry will always cause a global reset if the CPU V
DD
source drops below it’s fixed
threshold of 1.4V. However, the LVD trigger threshold to cause a global reset for the I/O
ring’s V
DDQ
source is set to one of two different levels, depending on the V
DDQ
operating
range. If V
DDQ
operation is at 2.7V to 3.3V, the LVD dropout trigger threshold is 2.4V. If V
DDQ
operation is 3.0V and 3.6V, the LVD threshold is 2.7V.