ST STR730-EVAL, User Manual, Page: 15 / 29

UM0559 Connectors
15/29
3.3 Debug
Figure 9. JTAG standard interface: CN1
Note: In order for hardware and JTAG RESET to be synchronized, (R3, R6, R5,C2,TR2, TR1)
have to be fitted, see
Figure 16: ARM JTAG interface on page 25 .
3.4 Input/output summary
Table 8. JTAG interface pinout: CN1
Pin Description Pin Description Pin Description
4, 6, 8, 10, 12,
14, 16, 18, 20
Ground 5 TDI 13 TD0
1 VTref +5 V 7 TMS 15 notReset
2 V5 V 9 TCK 17 DBGRQS - pulled low
3 notTRST 11 RTCK (GROUND) 19 DBGACK - pulled low
1
2
3
4
5
6
7
8
9
10
11
12 14 16 18 20
13 15 17 19
Debug-JTAG port
Table 9. STR730-EVAL board input/output summary
Port Peripheral Alternate function Interrupt
P0.0 LCD_D0 OCMPB2
P0.1 LCD_D1 OCMPA2
P0.2 LCD_D2 ICAPA2
P0.3 LCD_D3 ICAPB2
P0.4 LCD_D4 OCMPA5
P0.5 LCD_D5 OCMPB5
P0.6 LCD_D6 ICAPA5
P0.7 LCD_D7 ICAPB5
P0.8 LCD_RS OCMPA6
P0.9 LCD_nE OCMPB6
P0.10 LCD_RW OCMPA7
P0.11 TP52 OCMPB7
P0.12 TP53 ICAPA3