ST STM32U575I-EV, User Manual, Page: 72 / 105

7.29.4 I/O restriction to other features
Caution: Due to the sharing of some I/Os of STM32U575AII6Q by multiple peripherals, the following limitations apply in
using the LCD feature:
•
FMC interface is shared with SRAM.
7.30 Camera
7.30.1 Description
The CN16 40
‑
pin 1.00 mm pitch female connector is designed to connect the MB1379 CMOS camera
daughterboard supporting the DCMI interface.
The CMOS camera daughterboard is composed of the QSXGA 5 Mpixels CMOS camera with a dedicated
24 MHz crystal.
7.30.2 Operating voltage
The MB1379 CMOS camera requests a 2.8 V supply for the analog part and I/Os compatible with 1.8 to 2.8 V
voltage. For DCMI signals from the camera to MCU, a 2.8 V I/O level is considered enough to show a HIGH state
for a 3.3 V I/O.
For the signal from MCU to the camera, meaning the I
2
C interface, two MOSFETs are used on this interface to
drive I
2
C between 3.3 and 2.8 V camera.
7.30.3 Camera interface
The camera daughterboard cannot be operated simultaneously with the Octo
‑
SPI2 Flash memory. To use the
camera daughterboard, keep Octo
‑
SPI2 Flash memory unselected (PI5 chip-select HIGH) or removed JP20
from Octo
‑
SPI2 Flash chip select signal (R195 external pull up resistor keeps Octo
‑
SPI2 CS Flash memory
signal HIGH). To have a clear bus interface, remove the Octo
‑
SPI2 Flash memory solder bridge. Refer to
Section 7.23 Octo
‑
SPI2 Flash memory device for further details.
STM32U575I-EV
Camera
UM2854 - Rev 1
page 72/105