ST STM32L4 Series, User Manual

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Table 61. GFX_SM_1
SM CODE GFX_SM_1
Description Periodic LUT read-back
Ownership End user
Detailed implementation
This test is implemented by executing a periodical read-back of the LUT programmed memory
cells versus their expected value. LUT reference values are usually stored in the Flash
memory, allowing the implementation of the check feature.
Error reporting Depends on implementation
Fault detection time Depends on implementation
Addressed fault model Permanent/transient
Dependency on Device configuration None
Initialization Depends on implementation
Periodicity Periodic
Test for the diagnostic Not applicable
Multiple-fault protection CPU_SM_0: Periodic core self-test software
Recommendations and known limitations
Alternative solutions (such as reading LUT values and computing CRC seed to be checked
versus its expected value) are allowed.
End user must carefully check the MMU performance
impact loss due to read operations related to this method.
3.6.14 Extended interrupt and events controller (EXTI)
Table 62. NVIC_SM_0
SM CODE NVIC_SM_0
Description Periodic read-back of configuration registers
Ownership End user
Detailed implementation
This test is implemented by executing a periodic check of the configuration registers for
a system peripheral against its expected value. Expected values are previously stored in
RAM and adequately updated after each configuration change. The method mainly addresses
transient faults affecting the configuration registers, by detecting bit flips in the registers
contents. It addresses also permanent faults on registers because it is executed at least once
per
PST (or another timing constraint; refer to
(1)
in Section 3.6 Hardware and software
diagnostics ) after an update of the peripheral.
Method must be implemented to any configuration register whose contents are able to
interfere with NVIC or EXTI behavior in case of incorrect settings. Check includes NVIC vector
table.
According to the state-of-the-art automotive safety standard ISO26262, this method can
achieve high levels of
diagnostic coverage (DC) (refer to ISO26262-5:2018, Table D.4).
An alternative valid implementation requiring less space in SRAM can be realized on the basis
of signature concept:
•
Peripheral registers to be checked are read in a row, computing a CRC checksum (use
of hardware CRC is encouraged).
• Obtained signature is compared with the golden value (computed in the same way after
each register update, and stored in SRAM).
• Coherence between signatures is checked by Application software – signature
mismatch is considered as failure detection.
Error reporting Depends on implementation
Fault detection time Depends on implementation
Addressed fault model Permanent/transient
Dependency on Device configuration None
UM2305
Hardware and software diagnostics
UM2305 - Rev 10
page 40/110