Clocks
AN2586 - Application note
2.4
Clock security system (CSS)
The clock security system can be activated by software. In this case, the clock detector is
enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
●
If a failure is detected on the HSE oscillator clock, the oscillator is automatically
disabled. A clock failure event is sent to the break input of the TIM1 advanced control
timer and an interrupt is generated to inform the software about the failure (clock
security system interrupt CSSI), allowing the MCU to perform rescue operations. The
CSSI is linked to the Cortex™-M3 NMI (non-maskable interrupt) exception vector.
●
If the HSE oscillator is used directly or indirectly as the system clock (indirectly means
that it is used as the PLL input clock, and the PLL clock is used as the system clock), a
detected failure causes a switch of the system clock to the HSI oscillator and the
disabling of the external HSE oscillator. If the HSE oscillator clock (divided or not) is the
clock entry of the PLL used as system clock when the failure occurs, the PLL is
disabled too.
For details, see reference manual UM0306 available from the STMicroelectronics website
www.st.com.
