ST STM3221G-EVAL, User Manual

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Hardware layout and configuration UM1065
6/65 Doc ID 018640 Rev 4
2 Hardware layout and configuration
The STM3221G-EVAL evaluation board is designed around the STM32F217IGH6
microcontroller with a cryptographic acceleration cell in the UFBGA176 package. The
hardware block diagram
Figure 2 illustrates the connection between STM32F217IGH6 and
peripherals (Camera module, LCD, SRAM, EEPROM, MEMS, USART, IrDA, USB OTG HS,
USB OTG FS, Ethernet, Audio, CAN bus, smartcard, MicroSD Card and motor control) and
Figure 3 will help you locate these features on the actual evaluation board.